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Virage adds I/O cells to complete 'silicon platform'

Posted: 23 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:virage logic? i/o cell? base i/o? ip core? high speed i/o?

Virage Logic Corp. is finalizing its strategy for being a one-stop intellectual-property (IP) supplier by rolling out I/O cells as the final piece of a "silicon platform" aimed at companies developing SoC products.

Virage is teaming with high-speed I/O interface IP vendor TriCN Inc. to complete its offerings, which also include embedded memory and programmable logic cells. Built for both flip-chip and bondwire implementations, the I/O ring package has built-in noise isolation for improved operation and reliability for high performance applications, the company said.

The new line is being called Base I/O and will include cells for SSTL-2 Class I and II, HSTL Class I and II, PCI-X 1.0, PCI 2.2, 2.5V LVTTL and 3.3VLVTTL/CMOS.

The complete library will first be available on foundry TSMC's 0.13?m process.

The addition of the I/O cells fills a gap in Virage's strategy for being a complete IP provider. IC package design is increasingly frustrating chip designers, who must quickly work through the challenge of matching their complicated SoCs with advanced packages, such as FCBGAs that could have more than 2,000 pins and I/Os in the GHz range.

The complexity of such marriages is stirring industry debate about chip-package co-design, but little progress has been made. Last month, at the International Symposium on the Quality of Electronic Design, experts lamented the slow pace of development and urged the industry to encourage chip and packaging designers to work together early on to assess the system-wide impact of certain packaging scenarios.

Virage is hoping to appeal to designers caught up in this debate and who feel squeezed by the dense and varied I/O requirements. Packaging "is a very complex and rapidly growing market," said Brani Buric, senior director of product marketing at Virage. "There are more and more problems, which are essentially at the system level, where chip designers have to deal with I/O functionality."

Because changes in packaging standards are outpacing those for basic SoC methodology, driven by the need to address system-level design challenges such as performance increases, process temperature and voltage variations, and flexibility in package types, Virage will extend its I/O offerings by teaming up with other companies.

"We realized that it is almost impossible from a business or practical perspective, for Virage to try to address every part of the marketplace," Buric said. During the next few months, Virage will bring in more companies to its alliance.

Virage said its complete IP library is now available on Taiwan Semiconductor Manufacturing Corp.'s 0.13?m logic process. Front-ends are available immediately with pricing starting at $120,000. Other foundries and processes will be introduced over the next nine months.

- Mike Clendenin

EE Times

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