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TSMC will expand test, assembly services to spur demand

Posted: 23 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:tsmc? ic test? chips?

In an effort to remove barriers to chip production, Taiwan Semiconductor Mfg Co. Ltd will announce an expansion of its test and assembly services and additional guidance for chipmakers on how to prevent manufacturing delays.

Both topics, which will top the agenda at the company's annual technology symposium, show how the world's leading semiconductor foundry is relying more heavily on services that support its core chip production business as it tries to spur demand for its most advanced process technologies.

Putting more emphasis on back-end services, TSMC will announce ways on how it is expanding its in-house packaging and test capabilities as well as strengthening relationships with third-party companies in the areas of wafer bumping, wafer sorting, and flip-chip packaging.

"We're seeing that the integration of back-end services like assembly and test are going to be absolutely critical going forward as we move to low-k materials and sub-100nm technology," a TSMC spokesman said.

TSMC also is looking to become more involved in the design of a chip before it goes to production. Since some customers struggle with characterizing newer process design rules, TSMC said it wants to help them design high-yielding devices without having to re-spin their designs - part of the emerging design-for-manufacturing discipline.

"You're going to see us talk about design-for-manufacturability as it applies to libraries and IP [intellectual property]," the spokesman said. "The libraries are developed hand in hand with the process technologies, and by that starting point they have a strong design-for-manufacturability bent."

The efforts come at a time when TSMC is facing weaker-than-expected demand for some of its most advanced processes. A year ago the company predicted that it would ship 200,000 wafers with chips based on 0.13?m design rules by the end of 2002. The company now said it was able to ship only 100,000 such wafers by the end of March 2003 because of low demand. Unfavorable economic conditions and difficulties qualifying the process technology are to blame, said the spokesman.

"Production is as much driven by demand for the process as the technical ability to fire up the boiler and run it," he said. "At 0.13-micron, everyone knows we're dealing with new transistor sizes, copper and low-k [intermetal dielectric materials]. When you stand back and look at it, 0.13?m turned the world upside down."

Flash memory chip vendor Silicon Storage Technology Inc., for one, is in no rush to move to 0.13?m design rules, at least for low-density parts. The company, which has licensed its flash technology to TSMC, introduced a 4Mb Flash chip with a supply voltage of 1.8V.

The company employed its inherently low-threshold voltage memory cell architecture to bring down the voltage using more mature 0.25?m design rules. And it would make little sense to shift to a more advanced process because the die size would be disproportionately small compared with the surrounding bond pads, said Jason Feinsmith, business development director for SST.

Such hesitancy to migrate to 0.13?m design rules has caused TSMC to reconsider its rollout of a related process module. Last year the company had planned to introduce a second version of its high-speed 0.13-micron logic process, called HS+, but it canceled those plans when there were too few takers. Instead, all customers needing high-performance logic transistors will use the company's LV process, which is now in full production, the spokesman said.

Other modules have been delayed. A low-voltage version of TSMC's Emb-1TRAM technology, based on a memory cell approach from Mosys Inc., has been pushed out a year, until late 2003, as has a high-density version known as Embed1TRAM-X, which should roll out in Q1 of 2004. And a full-featured mixed-signal module that was originally scheduled for introduction in late 2002 will not be ready for "a couple of months," the spokesman said.

Analog intellectual-property vendor Barcelona Design Inc. said it will hold off on using the full-featured mixed-signal process as long as possible in a bid to save costs. Instead it is using TSMC's logic-based mixed-signal module for its latest PLL engines based on 0.13?m design rules.

"There are no restrictions on the PLL for logic. Where it gets tricky is for data converters, but we've got some unique ways to get around that and put it into a logic process," said Amit Nanda, director of business development at Barcelona Design.

Still, Barcelona's decision to shift to 0.13?m design rules is a sign that demand for the process node is picking up. Customers in Asia and Europe still tend to use more mature process technologies, "but in the U.S. [customers are] very much geared toward 0.13?m from a design-start perspective," said Nanda.

SST too said it is working with TSMC to develop high-density flash chips that will be based on 0.13-micron design rules. These devices, which would start at 64Mb densities, could appear next year, Feinsmith said. The TSMC spokesman said it expects to start qualifying parts with embedded flash technology from SST in Q4 of 2003.

Still others are already working on their second wave of devices using TSMC's 0.13?m process technology. Intrinsity Inc. qualified a 2GHz MIPS processor based on TSMC's LV process last November; now it plans to spin out a 1GHz version that consumes just 5.5W by the end of the year. Intrinsity CEO Paul Nixon said it will pull off that feat by using the same LV process and cutting the supply voltage to less than 1V.

There are also signs that chip vendors are getting a handle on the low-k dielectric materials that have vexed the industry during the past few years.

In recent weeks, both LSI Logic Corp. and Agere Systems Inc. have announced chips coming out of TSMC that employ intermetal dielectric materials with a k-value of 2.6, which is at the lowest end of the k-value range, according to the spokesman for TSMC.

- Anthony Cataldo

EE Times





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