Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

PrimeTime tool steps up to 50 million gates

Posted: 25 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:synopsys? primetime? static timing analyzer? gate analyzer?

A new release of Synopsys' PrimeTime tool, the EDA industry's most widely-used static timing analyzer, claims a runtime performance boost of two- to seven-fold over previous releases. Synopsys claims the new capability enables "overnight" signoff of 50-million gate designs.

According to customer benchmarks cited by Synopsys, the new PrimeTime 2003.03 release verified an 8-million gate design in two hours, and handled a 5-million gate design in one hour and 15 minutes.

Part of Synopsys' Galaxy IC design platform, PrimeTime offers full-chip, gate-level static timing analysis coupled with an integrated delay calculator and modeling capabilities.

According to the latest Dataquest Market Trends report, Synopsys held 71 percent of the timing analysis market in 2001. The report noted, however, that standalone timing analysis tools are declining in revenue, as more designers move to integrated IC implementation platforms.

- Richard Goering

EE Times

Article Comments - PrimeTime tool steps up to 50 millio...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top