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Samsung considers embedding FPGAs in ASICs

Posted: 28 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:samsung? fpga? asics? application specific ic? chip design?

Samsung Electronics' semiconductor division announced it may embed FPGA blocks in future ASICs as a way to reduce the time and cost of chip design.

Samsung is now in discussions with a number of FPGA companies and EDA providers about the pros and cons of embedded FPGAs, which will allow designated logic gates to be programmed after a chip has been fabricated and packaged.

The technology would let Samsung's ASIC customers design a single device that could be used across multiple product lines. Samsung may also design its own standard products in this way, officials said. The company further said it would discuss its views during a technical session on embedded FPGAs at the 2003 Embedded Systems Conference in San Francisco.

"We find that it's almost impossible to define the perfect product for customers. In many cases they want to add their own encryption technology, for example. For that reason we think having pieces of programmable logic embedded in an ASSP or ASIC makes sense," said Benson Cheung, director of business development at Samsung Semiconductor.

The company could design, for example, a communications chip that works either in a DSL or cable modem. "You can imagine a programmable block that can do either QAM encoding and decoding or DMT," said Bob Burke, marketing director for Samsung's system LSI division.

To go this route, Samsung needs two major components: an FPGA fabric and a design methodology. On the hardware side, the company said it will consider acquiring technology from or partnering with vendors making standard FPGA chips, including Altera, Actel, QuickLogic, and Xilinx. The company is also talking to smaller players promising new approaches, such as eASIC and Leopard Logic.

Considering options

One option would be to use technology similar to that offered by Actel and QuickLogic, which use programmable vias to attain high density. Another would be to partner with either Xilinx or Altera, the two top FPGA providers, which use a reprogrammable SRAM-based approach and own most of the patents related to FPGA technology.

The two companies' strong patent portfolio "may be one of the reasons that, if we decide to do this, we may partner with one of the larger guys than one of the smaller guys in the market," said Cheung, who once worked in Altera's marketing division.

Xilinx is now working with IBM Microelectronics under a non-exclusive contract to embed FPGA blocks in ASICs from IBM starting at the 90nm process technology node. Altera said it has the means to embed FPGAs, but has so far steered clear of this approach, preferring instead to promote its concept of a "system on a programmable chip."

On design methodology, Samsung is talking with "all the major players" to come up with tools for mapping an FPGA fabric to an ASIC and achieving timing closure, Cheung said.

Samsung executives stressed however that they have not decided on what approach to take, nor are they certain that embedding FPGAs is the right approach. One potential barrier is cost.

Customers "will pay a 10 percent or so premium for this product and it will have to ship in the hundreds of thousands or millions of pieces per year," Cheung said.

If it decides to use embedded FPGA technology, the technology would likely come on stream at the 90nm process technology node, which is now under development. At that point it would be less expensive to embed FPGA gates in an ASIC.

It could also help defray the costs of the mask sets, which will be in the $1.5-million range, Cheung said.

- Anthony Cataldo

EE Times

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