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EDA, test vendors ponder interoperability at DATE

Posted: 02 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:design automation and test? date? eda? test? ip?

The chasm between EDA and test vendors continues to be a vexing problem, with each side arguing that the other should try harder to close the divide.

Caught between them, intellectual property (IP) providers must work with EDA tool vendors and test companies to find ways to make designs testable.

All three sides in the ongoing and seemingly intractable dispute recently sat down to air their views. Not surprisingly, the session at the Design Automation and Test in Europe (DATE) conference ended up more as a United Nations-style show of diplomatic position taking than as any real forum for the resolution of integration issues.

Yervant Zorian, chairman of DATE's test-partitioning and SoC test committee, brought together EDA's big three vendors, Cadence, Synopsys, and Mentor Graphics, and three test companies, Teradyne, LTX, and Inovys. Sitting between them, figuratively if not literally, were IP providers LogicVision and Intellitech.

"We were hoping to enlighten the audience about the views of EDA and ATE executives on test," said Zorian, chief scientist at Logic Vision, who co-moderated the forum with EE Times' Nicolas Mokhoff. "With the increasing number of liaisons between design for test providers and test equipment companies, an update on their views is very timely."

Bridging the divide

Cadence's Rahul Razdan, corporate VP for system functional verification, told the panel that to bridge today's division, toolmakers and testers must understand each other's responsibilities. "On the system-design side, there is a need to be aware of all the elements that make up what I call manufacturing-aware design. And on the test side, one needs to be aware of all the requirements for design-aware manufacturing."

Antun Domic, SVP and GM of the Nanometer Analysis and Test business unit at Synopsys, said it was essential to reduce test costs and increase quality. Typically, he said, a chip today is built at 130nm and below, has more than 10 million gates and runs in excess of 300MHz. Since a chip like that carries a price tag above $10 million and includes hard-to-test complex mixed analog/digital blocks, "the high-level goal should be an automation and interoperability environment" from design through production, Domic said.

Among EDA's three biggest vendors, Synopsys may have the broadest engagement with ATE vendors. Specifically, Synopsys automates the closed-loop diagnostics flow between an ATE and its TetraMax for ATPG processing using the IEEE 1450 Standard Test Interface Language (STIL). "We are committed to STIL and to the CTL [the proposed common test language of IEEE 1450.6]," said Domic.

The test company representatives all insisted their links to EDA are available and ready to roll, but only if the links are specific to their individual equipment. "I don't believe that an open architecture will resolve the EDA-to-test issue," said Marc Levine, VP of the Enabling Technology Group at Teradyne. "Innovation is stifled this way. Why should anybody try to develop a 2ns tester when everybody has settled on a 6ns open-architecture tester?" Levine reiterated the common ATE-industry mantra: Open architectures should be open for each vendor's equipment to work with all EDA tools. It is not necessary, test vendors insist, that each EDA tool interoperate with each test tool.

Caught between EDA and test, IP providers are finding that embedding test structures into chips is one way to make the devices easier to test. "Embedded tests in chips can reduce the time-to-market substantially," said Vinod K. Agrawal, president, CEO and founder of LogicVision, a provider of infrastructure IP designed to ease IC test. "The six to nine months needed to debug a typical ASIC can be done in a month," he said.

- Nicolas Mokhoff

EE Times

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