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CoWare to unveil native SystemC tool

Posted: 07 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:coware? systemc? convertensc system designer? verification tool? system level design?

CoWare Inc. will release what it calls the first system-level design and verification tool built specifically for SystemC. The ConvergenSC System Designer product provides architectural design, simulation and analysis capabilities, CoWare said.

Like other vendors, Co-Ware had previously added SystemC support to existing products. But ConvergenSC (pronounced "convergency") is different because it includes a new data model that allows native SystemC implementation without the restrictions posed by SystemC add-ons to existing tools, the company said.

"We believe we're the first company to provide a from-the-ground-up SystemC tool that allows people to use the full power of SystemC inside a professional tool flow," said Pete Hardee, director of product marketing at CoWare. Add-on tools, including the SystemC capability available for CoWare's N2C design system, require users to cope with slow simulation and language subsets mandated by existing tools, he said.

ConvergenSC System Designer offers similar capabilities to CoWare's N2C System Designer, which supports architectural design and simulation. CoWare will continue to market N2C as a solution for ANSI C design.

The ConvergenSC System Designer lets users create "transactional prototype" models for processors, buses, memories, logic and software; run a SystemC simulator that CoWare says is five times faster than the Open SystemC Initiative reference simulator; and use analysis capabilities to view bus transactions, cache hits and misses, and processor utilization.

But the tool does not have an automated path to VHDL or Verilog. Unless users want to use SystemC all the way down to RTL design, they'll have to manually recode SystemC models in VHDL or Verilog. Automatic translation is "an obvious way to go" for future releases, Hardee said.

The transactional prototype models let designers make architectural decisions such as hardware/software partitioning, processor choice, co-processor design and bus characteristics. For custom processor design, CoWare's LisaTek software can generate instruction-set simulators that plug into ConvergenSC.

Transaction-level models allow designers to quickly raise the level of design abstraction, said Mark Milligan, CoWare's vice president of marketing. "You can construct a transactional prototype and boot an RTOS in tens of minutes in software simulation," he claimed.

CoWare this week will also announce the Amba Transactional Bus Simulator (TBS), an off-the-shelf solution for using the Amba 2.0 bus specification in SystemC. The tool provides a cycle-accurate representation of the bus protocol, Hardee said. "That doesn't mean the whole design is modeled at a cycle-accurate level; it's up to the user to introduce as much accuracy as he wants," he said.

With the Amba TBS, Hardee said, a user can instantiate all of the layers and instances of the bus, hook up all devices connected to the bus and run a fast simulation. ConvergenSC analysis tools then show where the bottlenecks are, letting users reconfigure the bus to improve throughput. Hardee said that CoWare will develop other bus models over time.

The ConvergenSC System Designer will be available in June starting at $105,000. In addition to SystemC simulation, it supports co-simulation with HDLs. Initial products supported include Synopsys' VCS simulator, Cadence's NC-Sim simulator and Novas' Debussy debugger. A standalone version of the SystemC simulator is available now. CoWare will upgrade N2C System Designer customers to ConvergenSC System Designer at no charge.

- Richard Goering

EE Times





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