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Siliconix JFETs eliminate latch-up

Posted: 08 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:vishay siliconix? jfet? junction fet? field effect transistor? dual jfet?

Vishay Siliconix has released a new series of junction FETs (JFETs) that eliminate the problem of latch-up in amplifier designs.

Latch-up occurs when several JFETs on the same substrate form a parasitic that can turn on unexpectedly, causing excessive current to flow. The new series overcomes this by providing an exposed substrate connection via an external pin, allowing designers to bias the substrate with a positive potential to prevent a latch-up condition.

Monolithic dual JFETs are widely used as a front end for amplifiers in test equipment, industrial process equipment, military monitors, and other application where high-accuracy data acquisition is needed. Integrating two transistors on the same substrate ensures that the temperature of both channels is the same. As a result, performance is more evenly matched across the device's operating temperature range than in implementations with two single-die JFETs.

Available in SOIC-8 (SST series) and TO-78 (U series), the JFETs offer breakdown voltages ranging from -25V to -50V. Offset/drift voltage ranges from 40mV down to 5mV, thereby minimizing errors in front-end amplifiers.

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