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Analysis tool combines dynamic, static timing methods

Posted: 08 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:nassda? hanext? timing analysis tool? crosstalk analysis tool? dynamic timing analysis?

Nassda Corp. has announced the availability of the HANEX circuit-level timing and crosstalk analysis tool, which is targeted for use in digital designs of 130nm and below.

The tool analyzes the timing of circuit blocks and determines critical paths using a combination of dynamic and static methods to accurately capture the effects of nanometer silicon on circuit behavior. It is positioned to replace purely static analysis methods, which often fail to detect timing problems that arise from nanometer effects or return results that are too pessimistic.

HANEX provides an integrated verification solution that combines dynamic and STA methods. It finds critical paths in combinational, latch/flip-flop, and dynamic logic, and then simulates the entire critical path simultaneously, considering voltage-dependent capacitance, Miller capacitance, and nonlinear input slopes to provide better accuracy.

Among its timing checks, HANEX verifies setup and hold timing for sequential logic including crosstalk effects and using dynamic accurate clock tree analysis.

The tool's hybrid analysis capabilities allow it to provide a more realistic assessment of circuit behavior than traditional static methods. Conventional static analysis methods approximate coupling capacitors with grounded capacitors, exposing the results to increasing error with decreasing geometries. In contrast, HANEX's optional crosstalk analysis uses internal dynamic simulation on coupling capacitors.

In addition, proprietary concurrent signal propagation capability analyzes the impact of neighboring nets on circuit performance to capture the exact signal transition windows to provide accurate delay calculations.

HANEX also uses its hybrid capabilities to provide accurate clock net timing simulation. It automatically identifies and traces the clock net starting with a user-defined clock source. After it back-annotates the clock net with interconnect RCs, HANEX simulates the entire clock net dynamically with precise fan-out loading, storing clock arrival time and slope at every clock sink.

The tool supports a variety of device models and SPICE netlist formats and can generate timing data needed for IP characterization in digital ASIC flows. It supports the Sun Solaris, HP-UX, Microsoft Windows NT/2000/XP, and Linux platforms.





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