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Motorola's power IC process runs on 300mm wafers

Posted: 16 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:smartmos? smartmos8 mv? smartmos7 lv? power ic? rf ic?

Motorola Inc. recently unveiled the latest version of its SmartMOS power semiconductor process technology, promising it will deliver unprecedented levels of integration. The SmartMOS8 MV (for medium-voltage) process combines a voltage capability of up to 90V with power and analog functions, plus an ability to build logic and RF capability on the same die.

Early tests indicate that the process can lead to a 50 percent reduction in the size of a design, said Bob Baird, SmartMOS technology manager at Motorola's Semiconductor Products Sector.

"We have used some really novel engineering to get high-voltage performance and high-density logic onto the same device in a cost-effective manner," Baird said. A key innovation is the deep trench barrier that is used to separate devices on a chip. The barrier effectively isolates sensitive logic blocks from the high voltages required for regulating motors or adjusting solenoid coils.

Designs under way

"Products are already being designed for use with the process," said John Pigott, IC architecture manager at the semiconductor sector's analog products group. "Because of their complex nature, these tend to be custom ICs with many times more logic gates than possible with previous generations of SmartMOS."

These products will generally have multiple power-output stages ranging from hundreds of milliamps to a few amps at better than 40V/80V, according to the company.

The process will typically be used for applications in the automotive and industrial sectors, and in wireless communications--though parts incorporating RF capabilities are expected later on, Pigott said. Early examples include low-noise receivers that require high voltages for tuning varactors and Bluetooth receivers that incorporate output stages for driving actuators. For instance, an IC for a vending machine could include a Bluetooth receiver, high-power solenoid drivers and an MCU power supply.

The 0.255m CMOS-based process is being certified to run on 300mm wafers at Motorola's fabrication facility in Chandler, Arizona; that certification should be completed in Q4, according to Baird. Volume production is scheduled to begin in the middle of next year.

The logic density of SmartMOS8 MV is 20,000 gates/mm2, or double the density of SmartMOS7 LV. The bipolar Ft is 3GHz, compared with 0.6GHz on SmartMOS7 LV, and the maximum operating voltage has risen from 45V to 80V. The minimum feature size of the SmartMOS7 LV was 0.355m, vs. 0.255m on SmartMOS8 MV.

Deep trench isolation significantly increases the analog packing density of a chip by bringing devices adjacent to each other across the trench, Motorola says. This enables shrinks ranging from 50 percent for medium-voltage analog to nearer 70 percent for high-voltage analog components. Baird said power device size has shrunk by 30 percent and digital logic by 50 percent.

"The process is capable of making parts with few erroneous circuits - an important consideration when you are combining analog and power circuits on the same IC," Baird said. "Such high voltage is pretty outstanding from a 0.255m technology." The use of deep trench for achieving high-voltage isolation will put Motorola well ahead of competing processes for smart-power devices, he said.

- John Walko

EE Times

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