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Sagantec releases analog compaction tool

Posted: 16 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:Sagantec? anaconda? analog compaction tool? ic design tool? ic placement tool?

Sagantec Inc. has released a schematic-driven, constraint-based compaction tool for analog design.

According to the company, the new tool, called Anaconda, accelerates analog physical design by automating repetitive manual layout tasks and enabling analog design reuse. The tool claims to automate numerous tasks that previously required months of hand tweaking when creating analog IP targeting new process geometries.

The company said the tool automates a range of tasks including the placement and sizing of the layout for derivative blocks. Anaconda reads sizes and constraints from a schematic and then refines a given topology to automatically and accurately implement the specifications, resulting in a correct and complete layout, claims the company.

Users feed Anaconda constraints and schematics, then the tool's compaction engine reads the device parameters and topology constraints from the schematics. It then automatically decides all geometric details for correct-by-construction device placement and sizing.

The tool checks and guarantees symmetry, wire widths, matching, alignment, and correct design rules. The geometry engine and database at the heart of Anaconda incorporate expertise gained over Sagantec's years of migrating complex analog layouts, the company claims.

The tool has been made to work in concert with Cadence's schematic-driven Virtuoso XL 4.4x design system. With Anaconda, users can drive incremental engineering change orders from the schematic and can make topology changes using the Virtuoso layout editor.

Anaconda will be available in Q3 of the is year. Time based licensing starts at $55,000 per year.

- Michael Santarini

EE Times

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