Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Atrenta tool scans thousands of flops, targets low-power design

Posted: 21 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:atrenta spyglass rtl? spyglass low power? rtl?

Atrenta Inc. has released a new version of its Spyglass RTL predictive analysis tool targeted at low-power design. The Spyglass Low Power is claimed by the company to assist users in proactively developing power-efficient RTL code.

The offering incorporates Atrenta's engine that synthesizes a user's RTL and then performs a number of low-power design checks on it. Users can also run particular checks after certain portions of their RTL are developed. The tool reads the RTL, applies heuristic checks and then flags in schematic and RTL where potential problems are occurring. It also converts the RTL and scans the tens of thousands of flops to locate those that would most benefit from gating.

The tool also does a number of low-power-minded checks on data path, control, buses, and memory units in the design. It flags and provides guidance on such data path-oriented techniques as the possible use of latches where power-hungry units are selectively used, and points out possible applications of precomputation.

It is said to handle designs employing multiple power and voltage domains. A one-year license starts at $75,000.

Michael Santarini

EE Times

Article Comments - Atrenta tool scans thousands of flop...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top