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Zarlink analog PLL has six ultra-low jitter clocks

Posted: 22 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:zl30406? semiconductor? analog pll? optical line cards? sonet/sdh line card?

The ZL30406 analog PLL from Zarlink Semiconductor has six low-jitter output clocks for optical line cards that is claimed by the company to allow designers to shrink size, cost, and power of line card timing designs.

The device supports up to OC-48 data rates, and regenerates and multiplies clock signals to higher frequencies while also "cleaning up" jitter. It delivers four differential LVPECL clocks at 77.8MHz, a differential CML clock programmable to 19.4MHz, 38.9MHz, 77.8MHz, and 155.5MHz, and a single-ended CMOS clock at 19.4MHz.

It also delivers a 0.46ps rms jitter performance that exceeds Telcordia's GR-253-CORE jitter requirements for OC-3 to OC-48 optical rates, and the ITU-T's G.813 Option 1 and 2 requirements for STM-1 to STM-16 rates.

The device is available in 64-pin TQFP measuring 10-by-10mm and is priced at $44.15 (1,000-up).

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