Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

FPGA toolset adds C synthesis interface

Posted: 26 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:aldec? c language synthesis? fpga? active-hdl? celoxica?

Bringing C language synthesis to FPGA design, Aldec rolled out on May 21st its Active-HDL v6.1 toolset offering an interface to Celoxica's DK2 Design Suite. The interface lets FPGA designers use VHDL, Verilog, C/C++, and Celoxica's Handel-C languages in a unified environment.

Aldec said its Active-HDL toolset supports HDL and C from concept to implementation. Designers can use Active-HDL's design entry environment to develop code, then invoke both HDL and C synthesis tools from Active-HDL's design flow manager.

The Celoxica DK2 design suite lets users work with C/C++, SystemC, or Handel-C. It generates readable RTL code and device-optimized FPGA hardware.

Active-HDL's flow manager lets designers access and control the DK2 design suite directly from Active-HDL, and translate C-based designs to VHDL, Verilog, or EDIF. The designs can then be brought into Aldec's common kernel simulation environment.

C synthesis results from Celoxica are back-annotated in the Active-HDL environment, so users don't have to switch between applications. Synthesis results can be viewed in Active-HDL's synthesis log and modified to develop more efficient devices.

- Richard Goering

EE Times

Article Comments - FPGA toolset adds C synthesis interf...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top