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Hybrid FPGA/ASIC devices address market needs

Posted: 02 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? asic? hybrid fpga/asic? oem? cot?

Advanced 90nm process technology will make things better or worse, depending on the perspective. While mask charges continue to increase and design and tooling costs spindle out of control, every process node will make FPGA-based products more attractive. Silicon cost is no longer the main factor for majority of products, as amortized non-recurring engineering (NRE) costs, packaging and test become the dominant cost drivers.

Once believed as the panacea to lowering component costs, most OEMs are abandoning their internal customer owned tooling (COT) flows, and are reverting back to an ASIC style design flow.

FPGAs have a bright future for low-volume applications and in high-volume but low-complexity applications. For a growing number of designs, however, neither of these options seems to work. Latest statistics show that about 80 percent of ASICs never exceed 500,000 lifetime units. The median design complexity is currently about 1.2 million gates. Despite marketing claims of FPGA vendors, they have yet to crack the 1 million logic gate mark. The result is a growing number of ASIC users seeking viable alternatives.

The result of these trends is that there is a growing number of designs that cannot be addressed effectively with either ASIC or FPGA.

Current solutions

System companies demand flexible chip-level solutions that allow them to add value and differentiate their products. Shrinking product life cycles combined with rising performance and capacity requirements mandate the use of innovative IC technologies to meet these market requirements.

Traditional design approaches address some of the needs, but have significant shortcomings in other areas:

  • While ASICs provide a good price and performance trade-off, the huge ASIC design, tool and mask costs are prohibitive for most companies who cannot afford to invest millions of dollars in EDA tools, training and manufacturing costs. The lack of flexibility poses another problem as many applications have field upgradability as a critical requirement.

  • FPGAs address the time-to-market problem and lack of flexibility of ASICs, and avoid the steep investment in tools and NRE costs. However, high unit costs prohibit their use in cost-sensitive applications.

  • ASSPs as off-the-shelf products seem to provide a good trade-off in terms of upfront and unit costs, and usually offer an optimized implementation for a given application. However, the issue in many systems is that ASSPs cannot be customized to meet specific product requirements. It leaves little room for product differentiation, and divert a significant portion of the overall product margin from the OEM to the ASSP vendor.

    There are now attempts to use reconfigurable processor arrays to replace logic devices. The key issue with these architectures is the different design methodology and programming model. Users are required to start their development from scratch and cannot reuse existing IP blocks or design tools.

    Emerging alternatives

    The recent emergence of embedded programmable logic cores enables the creation of flexible and cost-effective hybrid device platforms. Design functions that are fixed or low-risk are implemented in an ASIC fabric while high-risk blocks and functions that require field upgradeability are placed into the FPGA cores. This partitioning provides FPGA-like design cycles and flexibility while achieving ASIC-like performance, power, and cost.

    As many chip markets continue to fragment, hybrid devices will offer a new alternative for designers to partition their design. In the past, designers were forced to partition their design into multiple devices to achieve the right trade-off between flexibility, performance cost and power. This partitioning had to happen early in the design process to account for long ASIC design cycles. With this approach, the system partitioning was usually sub-optimal and could not be changed at a later time.

    Costs are measured as total cost of ownership, taking into account unit cost and fully loaded NRE. Flexibility is measured as time-to-market and turnaround time required for incremental design changes.

    Hybrid ASIC/FPGA solutions enable the most effective trade-offs, as they allow users to tap on a wealth of existing IP blocks, methodologies and design tools. These devices allow instant design changes like FPGAs, while leveraging the more efficient ASIC logic for fixed blocks of a design. These characteristics make hybrid devices the next ideal step for products that otherwise fall into the market gap.

    Hybrids are particularly attractive to users in emerging markets such as China that often lack the installed infrastructure to handle complex ASIC flows and shy away from the required multi-million dollar investments. Hybrids offer this user base a new alternative to get started quickly and cost-effectively. Easy-to-use and inexpensive design flows, low NRE and unit cost will drive the rapid adoption.

    - Stefan Tamme

    Sales & Marketing VP

    Leopard Logic Inc.





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