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Tool analyzes power dynamically, at cell level

Posted: 02 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:redhawk-sdl? power analysis? physical power flow? redhawk-s? spice?

Apache Design Solutions Inc. has recently unveiled a dynamic, vectorless cell-level tool that it calls the next linchpin technology for power analysis. RedHawk-SDL, the company's second product, will put Apache on the map, said president and CEO Andrew Yang.

"This is the technology that drew me back into EDA management after spending years as a full-time investor in EDA companies," said Yang, a founder of Anagram Inc. who became an executive of Avanti Corp. after it acquired Anagram. "Over the last couple of years we've seen the industry launching tools that bring physical effects up earlier into the design flow. We've seen a physical synthesis flow, a signal integrity flow and now we are going to see a new flow: the physical power flow."

Keith Mueller, VP of worldwide marketing and sales at Apache, said that designers working with finer process line widths and higher gate counts and chip speeds are hoping to power chips with 1V. That quest raises a host of power issues that older tools are hard-pressed to address.

"With ASICs running at speeds around 650MHz, power has become a big problem. It is not that you just need to power up the entire chip, but with new silicon processes you burn holes in silicon," said Gary Smith, EDA analyst with research firm Gartner Dataquest. "You need tools to identify hot spots. I think Apache is leading the way in the power domain."

The company's RedHawk-S static cell-level tool, introduced last year, set the stage for RedHawk-SDL, which Yang called Apache's flagship product. Sequence Design Inc. recently released a cell-level dynamic power tool named CoolTime.

Existing vector-based dynamic transistor-level tools are accurate but have slow runtimes and small block-level capacity, Yang said. Static cell-level technologies offer greater runtimes and bigger block-level capacity, but are less accurate, he added.

RedHawk-SDL is designed to improve on these earlier offerings. The cell-level power analyzer runs as fast or faster than static cell-level tools but has a full-chip capacity and can run 4 million gates in 2 hours on a single CPU, Yang said. The tool uses statistical analysis techniques and an in-depth extraction format and simulation algorithm to find corner-case errors that are not easily detected by existing tools, he added.

RedHawk-SDL analyzes the effects of on-chip and package inductance, capacitance, as well as dynamic voltage and the effect of its drop on clock skew and timing. "Older tools can't detect many of these transient-switching effects like inductance, and certainly don't indicate how these effects hinder clock skew and timing," said Mueller. "As chips reach 650MHz, inductance effects start to become dominant."

Full-chip analysis

Inductance can affect not only adjacent wires but also wires on different parts of a chip. To more accurately account for these effects, power tools would ideally cover an entire design. Apache said RedHawk-SDL has run full-chip analysis on a 20 million-gate design.

"Block-based solutions require vectors and there's no way for any designer to give you a worst-case vector set for a full SoC," said Mueller. In addition, static power tools often require the use of guardbands and encourage the overuse of decoupling capacitors, which can be ineffective, he added.

The RedHawk-SDL tool addresses these issues with a mix of performance, capacity and accuracy, Yang said.

To deliver Spice-level accuracy, Apache developed a new library characterization format, the Apache Power Library, that holds more detail than standard formats such as .lib. "We had to do our own format to get the accuracy we needed to do transient waveform cell characterization," said Mueller. The format extracts data from the targeted silicon vendor's Spice netlist to characterize data, he said.

With RedHawk-SDL's embedded RLC extraction engine, "users don't have to use another tool for extraction in our flow," said Yang. "It is one of the reasons our tool is so fast."

- Michael Santarini

EE Times





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