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ASICs added to Synplicity's synthesis line

Posted: 30 May 2003 ?? ?Print Version ?Bookmark and Share

Keywords:synplicity? asic? amplify asic? lsi logic? synopsy?

Synplicity Inc. will expand into ASIC physical synthesis with a tool that competes against offerings from Synopsys, Cadence and Magma.

The tool follows Synplicity's announcement that it was working with LSI Logic Corp. to develop tools for RapidChip, LSI Logic's structured ASIC. Now, said John Gallagher, director of ASIC tool marketing at Synplicity, the product of that co-development effort, Amplify ASIC, is being released to LSI Logic customers and to the general ASIC design market.

Amplify ASIC is a 2G physical synthesis tool with more capacity than first-generation tools, combining design planning with physical synthesis, Gallagher said. Magma Design Automation Inc. announced a similar technology this month.

First-generation physical synthesis tools do not have design-planning features built into the physical synthesis environment, Gallagher said, so users have to start design planning with one tool, perform block-level synthesis with another, floor planning with a third, and then run physical synthesis to get placement-optimized gates.

"We don't think there should be a separate silicon virtual prototyping and a separate physical synthesis environment," said Gallagher. "Those functions should occur in one environment, and that is what we have with Amplify ASIC."

Gallagher said the tool can be used in a standard design flow, but has a built-in RTL design-planning feature that allows users to perform design planning through physical synthesis in one environment if they choose. Synplicity expects most designers to use some third-party point tools with Amplify ASIC, Gallagher said.

With Amplify ASIC, users feed RTL code to the tool and such industry-standard formats as lib., tech LEF, DEF, PDEF or Synopsys Design Constraints. Users then begin design planning, deciding where major functions will go, and do clock tree and power estimation.

"We've built in block-level placement to begin the physical synthesis process," said Gallagher. "Users then pass off the netlist to gate-level floor planning."

After deciding a layout, users direct Amplify ASIC to run synthesis to generate optimized gates. The tool also outputs the usual industry-standard formats.

The tool will generate, on average, 20 percent fewer gates than competing tools, saving area without a loss of performance, Gallagher said.

Borrowed features

Much of the tool and its block placement features came from Synplicity's Amplify FPGA tool, Gallagher said. The company added to and adjusted many of that tool's algorithms to suit standard-cell design, he said.

"We've had Amplify FPGA for four years now, so we are well-versed in placement algorithms," Gallagher said.

Amplify ASIC runs on a 64-bit OS

The new tool will compete head to head against Synopsys Inc.'s Physical Compiler and Cadence Design Systems Inc.'s PKS tool.

Gallagher said that Synplicity's tool includes most features found in competing physical synthesis tools but lacks signal integrity capabilities. Those will be added soon, probably at no charge, using technology acquired in the purchase last year of Iota Technology Inc., he said.

To make a more immediate and meaningful impact in the physical synthesis market, Synplicity is targeting customers of LSI Logic and other ASIC vendors, as well as designers new to physical synthesis.

"There are many designers who either have been not wanting to move to physical synthesis, because of the lack of a skill set, or [whose] designs just need it now," commented Gallagher. "We think we have something for those users."

The tool is aggressively priced, the company said, with a one-year subscription starting at $90,000, three-year terms starting at $130,000 and perpetual licenses starting at $230,000.

A one-year time-based license for the Amplify RapidChip software-a version specifically for LSI Logic customers-starts at $35,000, with six-month time-based licenses starting at $20,000.

-Michael Santarini

EE Times

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