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TransEDA debuts property verification tool

Posted: 05 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:transeda? pa-studio? property and assertion capture and validation tool? accellera property specification language? psl?

Reaching toward the next methodology level in verification, TransEDA announced a property and assertion capture and validation tool at the 2003 Design Automation Conference. The company's new PA-Studio is aimed at verifying complex FPGA, ASIC, and SoC designs.

Today, most verification is done with conventional testbench-driven simulation and analysis techniques. "Today's techniques do not place the bugs into context, so you don't know which are the important ones that you need to go after," said Keith Monserrat, CEO of the U.K.-based TransEDA.

PA-Studio also supports the industry-driven standardization of the new Accellera Property Specification Language (PSL), formerly known as IBM Sugar, as the de facto language for property development.

It enables designers to graphically create, verify, and debug properties and assertions, ensuring that the design specification is correctly captured in advance of the verification stage. It thereby is supposed to shorten the property development cycle time by building in correctness-by-design from the start. "Increasingly, designers, test and verification engineers, IP developers and integrators are using properties in their designs, and PA-Studio is the first product on the market that facilitates the early adoption of this methodology," claimed David Dempster, marketing executive at TransEDA. "The product is built upon a flexible, open architecture designed to support other property and assertion languages, as they emerge."

In operation, the tool relies on two components - the property generator and the waveform editor. The property generator has a graphical front-end that uses an intuitive drag-and-drop facility o capture properties from the signals that appear in the design's hierarchy so that designers do not need to have an in-depth knowledge of the PSL/Sugar language in order to generate properties.

It ensures that all captured properties are syntactically correct. For those designers with an in-depth knowledge of PSL/Sugar, properties can be entered in textual format, which further speeds up the creation/capture process. The property generator can also be used to create a block diagram of the hierarchical design before any HDL code is written so that properties can be developed at the earliest possible stage in the design flow, saving cycle time.

The waveform editor then reads simulation information from a value change dump (VCD) file produced during a logic simulation, and uses this information to validate a property. This graphical tool enables signals and clocks to be easily created, altering their relationship on-the-fly, and thus validating that the captured properties accurately reflect the design intent.

A results viewer graphically shows where matches, partial matches or failures have occurred within the VCD trace. Color-coding is used to direct the user to where matches or failures have been encountered, so that errors can be rectified before the design reaches the verification stage.

The tool will run on SUN Solaris 7, 8 and 9, Hewlett-Packard HPUX 11, RedHat Linux 6.2 and above, and IBM AIX 4.3 and above. "We expect to make it available for about $10,000," said Monserrat.

- Nicolas Mokhoff

EE Times





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