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ESL tools 'may be driven by verification'

Posted: 09 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:system level design tools? esl? design automation conference? dac?

Skyrocketing design complexity will create a market for electronic system level (ESL) design tools, according to participants in a panel session at the Design Automation Conference. But several said that ESL will be driven by verification, not by design implementation, as widely assumed until recently.

System-level EDA tools have been around for a long time, but have never claimed more than a small percentage of the overall EDA market. Ten years ago at DAC, electronic system design automation (ESDA) was a major theme, only to fade into the background in succeeding years. Panelists looked at why ESL didn't work before, and what's different now.

Gary Smith, chief EDA analyst at Gartner Dataquest, said that power users didn't really hit a "design gap" until last fall, when they suddenly discovered they couldn't use even half the available silicon at 90nm, which allows 100 million gates. "What we're faced with is the fact that we have to move up to the next level of abstraction," said Smith.

Why didn't ESL take off in prior years? "What we were doing wrong is that we needed to get there through verification," Smith said. He pointed to two products introduced this year at the Design Automation and Test in Europe (DATE) conference, Axis Systems' XoC and Cadence Design Systems' Incisive, as ESL verification tools that are helping define a new market.

Mitch Weaver, VP of marketing for Cadence's systems and functional verification group, said that ESL tools have thus far been limited to small niches, and hampered by lack of system-level verification tools and a standard language. Today, he said, the ESL market "is being driven by verification, not implementation."

Weaver showed how Cadence's concept of ESL verification rests with a "functional virtual prototype" that works at a transaction level, runs off executable specifications, and provides a complete, high-level verification model of the design.

Also stressing the verification angle was Steven Wang, co-founder of Axis Systems, who spoke of the need for concurrent hardware and software design and verification. This, he said, will allow the delivery of verified intellectual property (IP) that can easily be incorporated into systems. But Wang said that complete automation is a "dream," and he said that behavioral synthesis will remain a difficult process and is unlikely to catch on.

Serge Leef, general manager for SoC verification at Mentor Graphics, attributed ESL's past failures to the lack of a system-level design language and a bridge to implementation. That, he said, confined demand to system architects - a very small group of people. But today, he said, what's possible is an "iterative spec-to-RTL flow" that lets designers write algorithms and move them back and forth across hardware/software boundaries.

"As more people embrace platform-based design, there will be a new class of users, system designers," said Leef. Smith agreed. "We're seeing large groups of ASIC designers move up to the system architecture level," he said.

Guy Moshe, CEO and president of Summit Design, said that today's systems encompass "software running on hardware" and cannot be adequately represented at the register-transfer level (RTL). What's needed, he said, is an ESL design flow that includes both functional design and architectural exploration, and then goes on to partitioning and hardware/software specification.

"System-level design is also referred to as platform-based design," said Ivo Bolsens, CTO at Xilinx. He said that programmable "fabrics" are providing the foundation for platforms with millions of gates, and that two groups of designers will emerge - a fairly small number of platform builders, and a large number of people who use programming techniques to specialize platforms and create products.

Several panelists pointed to SystemC as a standard language that will help drive ESL. "System C is ES level, SystemVerilog is RT level," said Smith. "There's no confusion about this in Europe or Japan, but there's so much smoke in the U.S. that there's some confusion. If you want to try to create software in SystemVerilog, go right ahead."

- Richard Goering

EE Times





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