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PC, consumer apps get fast PLL macros

Posted: 16 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:phase locked loop? locknow? analog and mixed signal? intellectual property? jitter?

True Circuits Inc., a provider of analog and mixed-signal intellectual property (IP), recently introduced two PLL macros for 0.185m and 0.135m CMOS ASICs. The spread-spectrum and low-bandwidth PLL hard macros use a fast locking technology True Circuits calls LockNow.

The spread-spectrum PLL multiplies an input clock by an integer or fixed-point number to implement a frequency-spreading capability. This type of PLL lets a user implement spread-spectrum functionality with an ASIC, rather than with a separate part, and is useful in PC and consumer electronics applications in which output varies from 30 to several hundred megahertz. The True Circuits device has an adjustable bandwidth, spreading rate and spreading amount, said John Maneatis, co-founder, president and chief technologist at True Circuits.

The low-bandwidth PLL is designed to control jitter from system clocks originating from lower-quality crystals. This PLL effectively generates high-speed clocks required for processors and chip interfaces that require low-jitter performance. Bandwidth is adjusted as a precise fraction of the reference frequency and designers can dial in the desired amount of period jitter filtering.

Shrinking the bandwidth effectively lowers the time the clock takes to lock, Maneatis said. Locking quickly prevents overshoot and cuts power consumption in portables. "If you can't lock, the loop runs longer and you burn more power," he said. Applications include disk drive read channels.

Privately held True Circuits has specialized in PLLs since 1998, Maneatis said. The IP developer was built by Stanford University graduates Stephen and John Maneatis. Though numerous competitors now offer analog IP, including Artisan Components, Barcelona Design, Leda Systems and Faraday Technology, few have had the same impact in low-jitter PLLs as True Circuits, John Maneatis said.

Glitch energy

True Circuits said its LockNow technology can dramatically improve PLL lock times. True Circuits' technique depends on an in-path filtering of the glitch energy ordinarily attached to a PLL's input clock. Without this glitch energy, jitter is reduced and locking is faster, the companies said.

PLLs built in 0.135m CMOS, for example, consume only 7mW with a 240MHz clock, and register less than 1.7 percent jitter as the output of the clock is multiplied up to 4,096 times. Fast startup time requirements often support portable designs, where a PLL is powered down to save battery life and must lock quickly on wake-up.

The new designs support frequencies, multiplication factors and functions in CMOS processes from 0.255m to 0.135m at foundries such as Taiwan Semiconductor Manufacturing Co., United Microelectronics Corp. and Texas Instruments. The PLL license fee includes integration support from True Circuits to ensure a successful tapeout. The deliverables include GDSII, LVS Spice netlists, Verilog models, synthesis models, LEF and extensive user guidelines.

- Stephan Ohr

EE Times





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