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Memory verification needs fresh approach

Posted: 16 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:memory verification? simulation? symbolic simulation? formal equivalence checking?

Verplex's K.C. Chen believes that memory verifcation techniques have not kept pace with SoC evolution and that a new approach is needed for implementation and system-level verifcation.

K.C. Chen is chief technology officer at Verplex Systems Inc.
Memory verification techniques have not kept pace with SoC evolution. Simulation is prohibitively time-consuming, particularly at the transistor level. The more advanced technique of symbolic simulation is an improvement, but it requires manual testbench and constraint work, which introduces the potential for error. Both techniques require manual testbench creation, which is time-consuming and provides incomplete coverage.

Similarly, symbolic simulation fails to completely verify large designs since it cannot identify functional errors outside of the user-specified conditions. To handle complex designs, designers must constrain symbolic simulation to the point that little of the functionality is actually checked.

Formal equivalence checking does a thorough job of verifying embedded memory, using rigorous mathematical algorithms to prove that an RTL model's behavior is identical to its low-level implementation. It is orders of magnitude faster than simulation-based methods, provides exhaustive coverage and diagnostic information, and needs no manual testbench or constraint generation.

But memories are designed at the transistor level in SPICE, and equivalence checkers could not recognize complex SPICE memory circuit structures such as bidirectional RAM cells, dynamic logic or sense amps.

Equivalence checkers also demanded that RTL models representing embedded memories have structure similar to their low-level design implementations - an identical memory cell row-column organization, for example. Unfortunately, some circuit behavior cannot be easily described at RTL.

Equivalence checkers also leave a gap between implementation-level and system-level verification. Implementation verification using equivalence checking must be performed at the transistor level, while system-level verification is typically done at much higher levels of abstraction using simulation. This forces designers to create two RTL memory models - one for system-level simulation and another for equivalence-checking the implementation.

A new methodology for implementation and system-level verification has been developed that uses a library of parameterized memory models targeted for both levels and a verification methodology that instantiates those models.

These parameterized models are offered as RTL descriptions, using the parameters to specify lower-level memory structural and circuit characteristics. By interpreting parameter values corresponding to the implementation structure, equivalence-checking comparisons between register-transfer and transistor level can be readily achieved. This permits memory formal verification at the transistor level for the first time. It also enables automatic generation of simulation models that can be used for more accurate verification at the system level.

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