Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

NEC design flow to improve wiring delay estimation

Posted: 18 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:NEC Electronics? copper-interconnect? signal-integrity?

NEC Electronics Corp. and its subsidiaries NEC Electronics America Inc. and NEC Electronics GmbH have developed a new copper-interconnect modeling methodology. According to NEC, this methodology enables an accurate layout parameter extraction (LPE) of copper interconnect and is capable of achieving high-precision wiring delay estimation.

The concept of effective density (Deff) is adopted for this methodology and implements a calculation procedure in an EDA tool. Deff designates the interconnect density of an arbitrary point on the die. According to NEC, another feature of this methodology is its cost-effective interconnect cross-section modeling parameter extraction. This includes correlating interconnect cross-section observation results with resistance measurements using the newly devised test structures.

"As semiconductor design complexity soars with advances in process generation, interconnect characteristics variance and signal-integrity emerge as clear and present issues that need to be solved," said Kazu Yamada, general manager, Technology Foundation Development Division, NEC. "Being the first company to implement this new modeling methodology, we can now offer one of the most precise DSM design environments currently available."

Article Comments - NEC design flow to improve wiring de...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top