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Wintegra broadens Altera deal for NPU codesign

Posted: 23 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:Wintegra? Altera? network-processor? Stratix FPGA?

Wintegra Inc., the network-processor startup launched by several Motorola executives, announced an expansion of its relationship with Altera Corp. during the Embedded Processor Forum.

The expansion will define functions in a new "Universal Front End" UFE2 device based on the Altera Stratix FPGA. The UFE2 will be used in conjunction with new multi-service processors, the WinPath WIN777M6 and WIN770M6 devices, which combine four packet-processing "WinGine" cores in chips that can be configured with or without MIPS control-plane processors.

The two multi-service devices, along with two Ethernet-optimized processors called WIN787 and WIN780, all use quad-core processors and represent Wintegra's high end NPUs.

The announcement here represents the first architectural description of the four new processors and the Altera coprocessor, all of which will be available in Q4.

Robert Odell, VP of marketing for Wintegra, said it had used Altera's Stratix architecture with its current generation of NPU, the 777M4, which uses an optimized version of Stratix as an optional conversion FPGA. It also uses industry-standard HDLC controllers, inverse multiplexer devices, and circuit-emulation devices.

The new FPGA integrates HDLC, inverse mux and circuit emulation, hence becoming a mandatory co-processor for use in any multiservice switching design.

Wintegra sells its network processors as standard chips, directly to its OEM customer base. For the UFE2, however, it licenses intellectual-property cores for direct implementation in Stratix FPGAs, which are sold by Altera.

The reason why the second-generation UFE2 integrated many formerly discrete functions was to allow the 770 and 776 processors to handle all asynchronous transfer mode, frame-relay, time-division multiplexing, and Internet Protocol functions without external chips for channel control.

As a result, the Wintegra processors can handle up to 84 ATM User Network Interface or Inverse Mux ATM functions, up to 84 Point-to-Point Protocol or Multilink PPP functions and as many as 2,016 channels of structured circuit emulation or frame-relay (over DS-0) channels.

The processors aggregate to channelized OC-3 (155-Mbit) levels, and can be expanded to OC-12 (622-Mbit) support. The new processor family can support Multi-Protocol Label Switching.

"We were aiming for a multiservice design that could really handle any combinations of protocols over any number of T1 ports, not something that required the user to cluster some arbitrary number of T1 ports together," Odell said. "The WinPath runs the state machines for processing, while the UFE configures and assigns ports for different types of traffic."

The two new packet-optimized processors launched by Wintegra, 787 and 780, integrate dual Gigabit Ethernet media access controllers and 16 serial ports for data-centric traffic.

In all families of the Wintegra architecture, devices ending in "0" are pure datapath devices without a control-plane core, allowing designers to use external control processors. The NPUs ending in "7" integrate a MIPS 5Kc core, so that control-plane and datapath processors are integrated in a single chip.

- Loring Wirbel

EE Times





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