Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Structured ASICs rescue endangered species

Posted: 01 Jul 2003 ?? ?Print Version ?Bookmark and Share

Keywords:asic? fpga? structured asic? ip? platform?

Doug Bailey, Chip Express VP of Marketing, believes that structured ASIC can solve the problems related to non-recurring engineering charges and productivity.

Doug Bailey is Vice President of Marketing at Chip Express Corp.
ASIC vendors have introduced platform-based, structured ASICs as a solution to the problems of non-recurring engineering (NRE) charges and productivity. Theoretically, the vendor performs the difficult work - purchase of intellectual property (IP), integration, and verification - enabling the designer to type a few thoughts into a DC shell, magically generating a custom ASIC implemented on a low-mask-count metal-programmable array based on the ASIC vendor's platform.

However, the platform is tricky to define. In effect, the ASIC vendor must specify 90 percent of a customer's chip. The chances of getting more than 50 percent right are slim. Moreover, the supplier must get everybody to use the same platform. In reality, platform-based ASIC designers are left with a chip that is 50 percent useful and is also in the hands of the competition.

How about FPGAs with multiple CPU cores embedded in them? Unfortunately, they are a cheap way to make very expensive end-products. Performance between the cores and the FPGA logic that surrounds them is often mismatched. The data cruises the embedded-core autobahn at 400MHz before coming to a virtual standstill on the FPGA's dirt road.

Another approach, "soft" platforms - collections of integrated synthesizable IP for a specific application space - can come preverified, saving development time. But experience seems to show that designers who will pay $1 million per instance for the latest "hot" IP may pay only peanuts for code that would save months of design effort.

The nonspecific structured ASIC is therefore often the best way to go. The logic is 10 times denser than in an FPGA, which makes it 10 times less expensive. It is much faster as well. Mask costs and NRE are 15 percent to 20 percent of the standard-cell equivalent. Design effort and product risk are reduced by reuse of critical pre-designed components.

Structured ASICs are broad and nonspecific. They include much of the analog IP that customers cannot add for themselves, but not the digital IP that can be purchased or developed easily: CPU cores, interfaces and data-processing functions.

How about a physical metaphor? High, narrow platforms focus on a specific target application. Broad, low platforms don't reach a high level of completion, but provide the designer with features and flexibility.

Structured ASICs are low, broad platforms that make good business and technical sense to most designers. They don't enact the dream of 90 percent preverified technology delivered just as the customer required. But they deliver a solid base for starting a design with low up-front NRE and low implementation risk.

The ASIC business is caught between a rock and a hard place: expensive unit prices for FPGAs on one side and unreachable mask costs on the other. The new structured ASICs with high-performance, reasonable I/O flexibility and a ton of memory will help the endangered ASIC species to survive and thrive. Those high, narrow platforms are an expression of the problem and a manifestation of the industry's angst, but not a solution to any particular ASIC.

Article Comments - Structured ASICs rescue endangered s...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top