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Reconfigurable computing driving new era for DSP

Posted: 16 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:dsp? microprocessor? risc? asic? fpga?

Although DSPs have been around for considerably less time, their development has followed a similar pattern to that of the microprocessor. Like many early MPUs, the first DSPs were 8bit and had to be programmed in assembler. Application development was time-consuming and expensive, and good programmers were in short supply. Twenty years later, DSPs are typically 16bit to 24bit and for the most part, can be programmed in C.

However, just as conventional DSP technology is reaching a level of maturity that eases application development, new applications are emerging that conventional DSPs cannot adequately address. The cycle-count burden that prevented RISC MPUs from matching the real-time performance and low-power consumption of DSPs is now preventing DSPs from meeting the demands of new applications in areas such as wireless networking and mobile portable multimedia devices. What is needed in these applications is a new computing paradigm that retains the inherent programmability of a software-driven solution, while also achieving the raw processing speed and low-power consumption of a hardware solution.

That new paradigm is almost certain to be reconfigurable computing--a new approach to speed vs. power consumption vs. programmability dilemma that combines the 'computing in time' concept of current MPUs and DSPs with the 'computing in space' model of hardware ASICs and FPGA solutions. The important thing about reconfigurable processors is that they are capable of computing in time and space at the same time.

Reconfigurable processors typically comprise a 2D array of interconnected computing elements, each with its own ALU and local register storage, onto which tasks can be mapped spatially, temporally or a combination of both. Programmable connections between these computing elements allow the data flow architecture of the array to be dynamically reconfigured to optimize it for the specific task in progress.

Stretching limits

At one end of the spectrum, you can assign a single fixed instruction to each computing element and connect them together in much the same way that you would connect library cells together in an ASIC solution. At the other end, the array can be configured to run a sequence of software instructions, mimicking a conventional DSP. In between, all combinations are possible. An interesting example is that Philips is already investigating the use of reconfigurable computing to perform software-controlled demodulation of a radio receiver's IF--a task that stretches conventional DSPs beyond their limits.

As the industry begins to embrace this new paradigm of reconfigurable computing, one thing is certain--the industry will not be prepared to go back to the days of assembly language programming. To meet the short development times and software reuse demanded by Asian OEMs and ODMs targeting fast-moving consumer electronics markets, application programming must still be possible in high level languages such as C.

Compiler technology will therefore have to be perfected to the point where it can deal with the inherent architectural flexibility and parallelism of reconfigurable computing, while also being able to address real-time performance and code-size issues. Because reconfigurable computing gives application developers the ability to control the hardware and software architecture of their design, these compilers will be some of the first that are capable of true hardware/software co-design for systems requiring DSP implementation.

- Atul Sinha

CEO, Silicon Hive

Philips Technology Incubator

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