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Scalable DSP architecture heeds OEM's needs

Posted: 16 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:dsp? time-to-market? architecture? 3g? synthesizable core?

Leveraging existing software across various DSP applications is critical for accelerating time-to-market. This reality is particularly true for products developed in response to emerging standards, such as 3G wireless, where demand is growing dramatically for all forms of cellular handsets including voice, data and media-centric platforms.

With the advent of scalable DSP architectures, OEMs of digital handsets can now optimize their designs in terms of performance, power dissipation and cost, maximize their reuse of software and actually mitigate their project risk.

DSP architectures can be scaled in two ways:

1. With a single core supporting optimal trade-offs among performance, power dissipation and code size (cost) for a range of product applications.

2. With a single, synthesizable core that can address different performance needs by easily retargeting the DSP core to alternate fab processes with different levels of performance.

The article outlines some of the features of scalable DSP architecture teamed with a flexible instruction set to meet the demands of an entire product space such as a family of wireless handsets with differing performance requirements.

Scalable, single core

While 3G standards allow for higher data rates, there will still be demand for handsets that are voice centric--where products are differentiated by battery life and cost. The DSP core must provide a variety of control functions efficiently (resulting in compact code) and consume little power.

In other applications, 3G standards are driving handsets to be more data-centric or media-centric, where they support applications such as browsing simple text, viewing still pictures or video and providing voice communication. The DSP must provide these performance-hungry features and yet minimize their drain on the batteries.

To support the diverse performance, power dissipation and cost needs of a product space, such as with 3G wireless handsets, StarCore determined that a single DSP core must possess four key attributes: efficient compilation, performance, low-power consumption and compact code size.

Consequently, the company based its licensable DSP architecture on a 16bit orthogonal instruction set. Working in conjunction with the DSP core's five-stage pipeline, this programming model produces highly-efficient compiled code. For instance, StarCore benchmarked a C-language implementation of an adaptive multi-rate (AMR) vocoder on its scalable DSP and determined that the compiled code required 40 percent fewer execution cycles and 50 percent less code space than when compiled on a comparable, non-scalable DSP.

Since low-power consumption is such a strict requirement for wireless handsets, StarCore's DSP core architects went beyond providing the traditional low-power standby modes by including a power-efficient pipeline and dispatch unit.

Synthesizable cores

Today's sophisticated synthesis tools take into account more constraints than any designer would be able to, thus generating logic circuits with optimal timing (i.e., frequency), size (i.e., cost) and power consumption. Attempts to 'outsmart' the tools with explicit instantiations often yield inferior results. A technology-independent design presents the following advantages:

? You can retarget the design quickly and easily to different libraries and processes, thus achieving a shorter time-to-market.

? Thanks to fast synthesis, you can explore a large number of implementation solutions in a short time, and iterate this process until the exact desired results are achieved.

The core may be implemented in one process to meet the performance goals of infrastructure base station application requiring several hundred megahertz. The same core design can be re-synthesized using a low-leakage process to meet the lower performance and cost needs of a handset application, while providing ultra low battery drain. The results are a minimum investment in resources and time, higher efficiency and reuse of technology and improved time to profitability. You only pay for the performance you need for your application and you have the flexibility to quickly respond as performance needs change.

StarCore's family of DSPs employs variable-length execution set (VLES), which groups related instructions together to exploit the number and kinds of parallel execution units provided on the core. Performance of this magnitude is needed for wireless handsets that support MPEG-4 video, MP3 audio, VoIP or JPEG 2000 still pictures. The use of the VLES makes the most of the 16bit instruction set architecture (ISA) yielding much smaller code size. This has the added benefit of saving on system costs by requiring a smaller system memory.

When developing DSP applications for low-end to high-end products in the same space, OEMs are motivated to reuse application code to minimize their time-to-market, cost and risk. By utilizing a scalable DSP architecture, OEMs can now readily achieve these objectives.

- David Rosado

Marketing Manager

StarCore LLC





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