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Using FPGAs to break Moore's Law in signal processing

Posted: 16 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? dsp? moore's law? wireless? bandwidth?

Moore's Law has demonstrated the doubling of transistor count every 18 months for a given piece of silicon. However, in wireless applications, the name of the game is to fill more bits across a finite bandwidth.

Bandwidth is a fixed resource, hence the impetus to cram more bits into that finite spectrum. Algorithmic complexity, extracting ever more bits/hertz, actually rises faster than Moore's Law does. The cellular standards are representative of this increasing complexity where there was about three orders of magnitude increase in processing between first-generation and 2G, and another three orders of magnitude between 2G and 3G.

The trend for algorithm complexity (dubbed as Shannon's Law) to grow faster than Moore's Law is forecast to continue for at least the next generation of wireless, which will be using multiple input/multiple output (MIMO) antennas. Using MIMO, one can seemingly cheat the Shannon limit regarding the amount of information passed over a channel.

Most logic and other complex chips do not really scale at the full rate that Moore's Law would predict. This is because it gets harder to use transistors in constructive ways: for example, processors need to have pipelining and superscalar techniques added. However, it is important to note that FPGAs do scale relatively well with Moore's Law. In this respect, FPGAs act more like digital memory than processors or random logic devices.

We call the region between the processor curve and Shannon's Law the "FPGA Zone." This represents applications like 3G chip rate processing, wireless broadband, MPEG-4 and other applications that require more computing power than processors alone, and this is the area where FPGAs have seen great success in the DSP market segment.

This is a direct result of the fact that FPGAs attain their high performance by implementing DSP algorithms in parallel form. In other words, the performance of an FPGA scales directly with its area, just as the capacity of a RAM scales with area. This scalability of the FPGA means that FPGAs are expected to fulfill requirements in the "FPGA Zone" for the foreseeable future.

The key to successfully taking advantage of the full capabilities of FPGA-based DSP systems is in software - both for developing the underlying DSP algorithms and in the embedded software that runs on the final system.

Software development systems are key enablers for high-performance, FPGA-based DSP systems. Designers use software to unlock the full power of FPGA hardware, and the dynamic interplay between software and hardware becomes an important driver for accelerating system design. FPGAs combined with these new software tools can have a great impact on the next generation of DSP systems. These tools and this complete design flow allow DSP designers to break down the barriers to achieving Moore's law.

So how does the software world keep up with Moore's law? What really matters is the number of computational cycles or machine instructions per day. This number is forever being increased by higher levels of programming abstraction. The history of system design and software development is punctuated by these advances in abstraction.

These gains are possible for two simple reasons. One is that the output reflects the overall increasing capability of the hardware architectures. The other reason for productivity gains is the introduction of development tools that raise the level of design abstraction. This is a regular occurrence throughout the history of both software and hardware design.

To summarize, the challenges of high-performance DSP design can be addressed by a top-down approach that combines system-level design and automatic generation of the FPGA implementation.

- Wim Roelandts

President and CEO

Xilinx Inc.

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