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Networked multimedia success hinges on DSP selection

Posted: 16 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:networked multimedia? dsp? mcu? multimedia data? lan?

Selecting a DSP for networked multimedia applications is a complex endeavor. First, a thorough analysis of the processor's core architecture and peripheral set must be prepared in the context of present and near-term industry interface needs. Second, it is crucial to understand how multimedia data (video, images, audio and packet data) flow through a DSP-based system to prevent bandwidth bottlenecks. Moreover, it is helpful to understand the various system attributes that could make the difference between a marginal implementation and a robust solution.

The choice of processor for networked multimedia is determined by the performance and connectivity requirements of the design. Many applications use both MCU and DSP; the MCU provides the control functionality for the system while the DSP does the intensive numeric computation. Today, these distinct roles are united in a single processor. This type of device presents control code density and intensive signal processing in a single architecture, while offering a wide peripheral set suitable for multimedia connectivity.

Among the first measures that system designers should analyze when selecting a DSP are the number of instructions performed each second, the number of operations accomplished in each processor clock cycle and the efficiency of the computation units. The merits of each of these metrics can be determined by running a representative set of benchmarks on the DSPs under evaluation.

The results will indicate whether real-time processing requirements exceed DSP's capabilities, and whether there will be sufficient capacity available to handle new or evolving system requirements. Many standard benchmarks assume that the data to be processed already reside within the internal memory. This technique allows a more direct comparison between DSPs from different suppliers, as long as the designer reconciles the I/O considerations separately.

The right peripheral mix saves time and money by eliminating the need for external circuitry to support the interface. Networked multimedia devices (NMDs) draw from a universe of standard peripherals. Prominent among them is connectivity to the network interface. In wired applications, Ethernet is the most popular choice for networking over LAN, whereas IEEE 802.11a/b is emerging as the prime choice for WLANs. Many Ethernet solutions are available as a direct extension to the DSP. In addition to DSPs that can support MCU functionality equally well, a TCP/IP stack can be managed right on the DSP.

General purpose devices

Also necessary for linking the DSP to the multimedia system environment are synchronous and asynchronous serial ports. In NMD systems, audio codec data often streams over synchronous 8bit to 32bit serial ports, whereas audio and video codec control channels are managed via a slower serial interface such as SPI or a 2-wire interface. Furthermore, UARTs can support RS-232 modem implementations, as well as IrDATM functionality for close-range IR transfer.

Many DSPs provide a general purpose interface such as PCI or USB, since these can bridge to several different types of devices via external chips (e.g., PCI to IDE, USB to 802.11b, etc.). PCI can offer the extra benefit of providing a separate internal bus that allows the PCI bus master to send or retrieve data from the DSP's memory without loading down the DSP core or other peripherals. DSPs suitable for the NMD market will include an external memory interface that provides both asynchronous and SDRAM memory controllers.

The asynchronous memory interface facilitates connection to flash, EEPROM and peripheral bridge chips, while SDRAM provides the necessary storage for computationally intensive calculations on large data frames.

A new peripheral that has started to appear on high-performance DSPs is the parallel peripheral interface (PPI). This port can gluelessly decode ITU-R-656 data and act as a general purpose 8bit to 16bit I/O port for high-speed A/D and D/A converters or ITU-R-601 video streams. It can also support a direct connection to an LCD panel. Additional features that can also reduce system costs and improve data flow within the system are available. For example, the PPI can connect to a video decoder and automatically ignore everything except active video, effectively reducing an NTSC input video stream rate from 27Mbps to 20Mbps and sharply reducing the amount of off-chip memory needed to handle the video.

System data flow

Before reaching a final decision on the choice of DSP for NMD design, it is imperative to understand the system level data flow, and how that flow can be implemented on the DSP.

Can data be brought in and out of the processor without falling behind on data and signal processing? Can the processor be kept fed with data, and can the data be accessed as needed during any given processing interval? These questions are crucial in a multimedia, network-centric system, where running algorithms efficiently is not enough by itself; the DSP must also handle the complete bidirectional system data flow.

Consider the case of a security system where an NTSC camera streams video and audio into a DSP at around 20Mbps, where it is compressed and sent out over a 100Mbps Ethernet connection to be stored and archived in a remote disk drive. The uncompressed video is routed from the DSP to a local display. Because the video memory requirement far exceeds available on-chip memory, data must be staged and manipulated via some larger-capacity, off-chip memory like SDRAM.

Since many video compression algorithms operate on one block of data at a time, each block can be transferred as needed from external memory. Some algorithms require multiple image or video frames to complete the desired processing, resulting in multiple bidirectional data transfers between internal and external memory. An input buffer often streams into the SDRAM concurrent with the DSP core compressing data in the previous buffer. It is likely that these buffers will be on different pages within SDRAM. This can result in costly latencies unless the DSP allows more than one SDRAM page to be open at a time.

The security system scenario is a realistic depiction of the daunting data transfer rates that must occur between several subsystems to support networked multimedia applications; there are at least five sets of simultaneous data movements involved in the above example. When considering the overall dataflow, it is not sufficient to simply verify that the total byte traffic moving through the system does not exceed the DSP's theoretical internal bandwidth (obtained by multiplying the bus speed by the bus width). For instance, in parts with high-core clock rates, the buses between the core processor and the peripherals will typically be run at a rate of 133MHz.

With bus sizes of 32bits, the throughput should ideally approach 532Mbps. In reality, this peak number can only be achieved if exactly one transfer is active and no other transfers are pending. As individual peripherals are added to the application, they must each arbitrate for the internal DSP bandwidth. System designers typically allow arbitration delays by assuming that only 50 percent of the internal bandwidth is available.

It is clear that DSPs suitable for NMD applications must have a DMA engine that is independent of the core processor. That is, the total number of DMA channels available must support the wide range of peripherals. Additionally, a flexible DMA controller can save extra data passes in computationally intensive algorithms such as MPEG or JPEG processing. For example, data can be transferred between memory systems and peripherals in a variety of ways.

Moreover, DSPs with 2D DMA capability can facilitate transfers of macroblocks to and from external memory, allowing data manipulation as part of the actual transfer. This is a very handy feature for interleaving/de-interleaving color space components for video and image data without having to perform additional data moves prior to processing. To maximize the benefit of DMA, a prioritized interrupt controller is needed to insure the core is only interrupted when data is ready to be processed or when processed data has been successfully transferred out.

It should now be clear that processor selection for networked multimedia applications is a crucial and complex task. However, by taking system-level issues into account at the initial DSP selection stage, designers can not only guarantee that their present application data flows will be handled well, but will also ensure that processor headroom and peripheral connections exist for straightforward upgradeability as network and multimedia standards evolve.

- David Katz and Rick Gentile

Senior DSP Applications Engineers

Analog Devices Inc.

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