Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Lattice serdes transceiver suits SONET, 10GbE apps

Posted: 30 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:lattice semiconductor? SERDES transceiver? transceiver? cmos technology?

Lattice Semiconductor Corp. has released what it claims is the industry's lowest power SERDES transceiver that is based on the 0.13?m CMOS technology. Designed for SONET OC-192 and 10GbE applications, the XPIO 110GXS-01CF269C consumes 0.8W of power at 10Gbps.

The XPIO device generates and receives 10Gbps clock/data streams utilizing CML signaling over a single channel, reducing the number of connections needed. Offering a continuous operating range from 9.953Gbps to 10.709Gbps, the transceiver can also be used in 200-pin MSA- or 300-pin MSA-based optical transponder modules.

The device supports 16:1 serialization and 1:16 deserialization with a parallel LVDS data range from 622Mbps to 670Mbps supporting the Optical Internetworking Forum's SFI-4.1 and 10GbE XSBI standards. An on-chip low-jitter PLL generates all required clocks based on an external reference clock of 155.52MHz or 622.08MHz.

Offered in a 15-by-15mm 269-ball flip-chip BGA package, the transceiver is priced at $79 in 5,000-piece quantities. Evaluation kits are also available for $4,999.

Article Comments - Lattice serdes transceiver suits SON...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top