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WEDC SSRAMs reduce active memory device count

Posted: 08 Jul 2003 ?? ?Print Version ?Bookmark and Share

Keywords:white electronic designs? nbl ssram? no bus latency synchronous sram? w2z1m72sj35bc? w2z512k72sj35bc?

White Electronic Designs Corp. (WEDC) has expanded their NBL (No Bus Latency) Synchronous SRAM (SSRAM) portfolio with the release of the W2Z1M72SJ35BC (72Mb) and W2Z512K72SJ35BC (36Mb) devices. Providing high-density, speed and flexibility, the products allow OEM Design Engineers to reduce overall active memory device count, reduce power, and improve space utilization of their PWB.

The SRAMs employ high-speed CMOS fabricated silicon designs, and are designed to sustain 100 percent duty bandwidth during read/write transactions by eliminating the turnaround cycles associated with the memory device operation. All inputs are internally self-timed, with the exception of an Asynchronous Output Enable which are synchronized to the rising edge of input C/W operations.

The devices are JEDEC-pin compatible, Pipeline NBL, packaged in a 14-by-22mm 209BGA, and operate at 2.5V. The W2Z1M72SJ35BC is available in 1Mx72 configuration and is priced at $150, while the W2Z512K72SJ35BC is available in 512Kx72 configuration and is priced at $52, both in 1,000-unit quantities.

Lead time is 8 weeks.

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