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Substrate noise can tax tools, methodologies

Posted: 16 Jul 2003 ?? ?Print Version ?Bookmark and Share

Keywords:substrate noise? substrate modeling? tcad simulation? circuitry? coupling?

Raminderpal Singh, manager of Process Design Kit Development at IBM, says complex substrate-modeling, prediction methodologies and tools can all prove futile in IC design without understanding the "bigger" parasitic future.

Raminderpal Singh is manager of Process Design Kit Development at IBM

Substrate noise exists in virtually every IC design today. Noise injection from "aggressors" into the silicon substrate is almost guaranteed whenever digital circuitry or on-chip oscillators exist. The amount of injection is dependent on the FET (or bipolar junction transistor) device dimensions, the frequency and slew of the signal, as well as the device's output loading.

So what are designers worrying about? Primarily, it's unwanted substrate coupling to sensitive circuitry. The injected substrate noise (propagated as current, but measured and simulated as voltage through a substrate impedance) has a nasty habit of following the lowest AC path to ground. Notably, that path may lead to the far side of the die. Thus, substrate-noise coupling can be a global coupling problem.

Noise and coupling effects typically manifest themselves in three ways. First, sensitive active and passive devices pick up the noise from the substrate; second, interconnect signal power is lost to the substrate; and third, sensitive interconnect lines pick up coupling from the substrate. No doubt, there will be more manifestations, especially as frequencies ramp and effects such as thermal and radiation coupling become better understood and modeled.

Modeling is a challenge. The impedance model must be global in scope (that is, across the die), minimal in size to avoid simulation bottlenecks and aware of the noise frequency spectrum as the substrate impedance transitions from real to complex to imaginary in nature. Also, the substrate in itself is only a piece of a larger RLC model including the interconnects, the IC package and some of the PCB traces. Oftentimes, the designer must model all these pieces together to allow for accurate simulation data--a tough problem that is in itself hard to resolve holistically.

How should designers deal with this? Options include using commercial or university circuit-level substrate-modeling tools and methodologies; TCAD simulation tools; and test site results. Each approach has its merits and problems, and much depends on the time and money available to the design team. More importantly, a lot depends on the design team's expertise. In radio integration, for example, product design experience is a key factor to success that allows the design team to avoid the use of a tool altogether, perhaps by using substrate isolation data extracted from previous design runs.

It is not always enough to understand only the substrate-coupling effects in your design. Without an accounting of the "bigger" parasitic picture, complex substrate-modeling and prediction methodologies (and tools) may all be to no avail.

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