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IMEC launches programs to expand sub-45nm research

Posted: 18 Jul 2003 ?? ?Print Version ?Bookmark and Share

Keywords:imec? transistor? srb? cmos? transistor?

IMEC has begun two industrial affiliation programs (IIAPs) targeting the sub-45nm technology generations.

The first program aims at providing solutions for improved device performance by implementing strained Si in the transistor channel for scaled planar MOS devices. The program covers strained Si formation on top of SRB (Strain Relaxed Buffer) layers, silicide formation, shallow junctions and extensions, compatibility issues, advanced strain characterization, and device demonstration.

Meanwhile, the second program will exploit the high-mobility features of Ge to fabricate high-performance CMOS transistors. The programs are interlinked with IMEC's present advanced CMOS research programs, which aim at developing the enabling process and device technologies for future technology generations. It will explore a Ge-based technology to fabricate high-performance CMOS transistors in a process compatible with silicon baseline CMOS.

These programs will be closely interlinked with IMEC's current advanced material, process steps, and models research programs targeting the sub-45nm technology node. The programs are initially using 200mm equipment and will gradually transition to 300mm equipment in IMEC's new facility now under construction.

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