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Monterey Design receives patents on silicon prototyping, physical implementation

Posted: 25 Jul 2003 ?? ?Print Version ?Bookmark and Share

Keywords:Monterey Design? silicon virtual prototyping? physical implementation technology?

Monterey Design Systems has been issued two new U.S. patents entitled "Method for Design Optimization Using Logical and Physical Information" and "Method for Designing Large Standard-Cell Based ICs." The patents apply to the silicon virtual prototyping and physical implementation technology that enables the Monterey Progressive Refinement approach for multi-million-gate nanometer chips.

The silicon virtual prototyping patent applies to an automated method of designing large digital integrated circuits by partitioning the design into physically realizable partitions and then creating the connections between the partitions so as to maximize performance and routability while minimizing the die size. Meanwhile, the physical implementation patent covers a method for design optimization using logical and physical information by simultaneously performing logic optimization and placement using an open multi-objective cost function.

The patented technology has been incorporated in the company's recently launched CALYPSO product - a complete silicon virtual prototyper and Dolphin physical implementation system.





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