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Coexistence in a multilingual design world

Posted: 01 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:systemc? verilog? hdl? system verilog? ieee 1364?

Cadence Berkeley Labs' Grant Martin observes that while Verilog and SystemC are commonly depicted as opposites, both have complementary roles in moving designs from specification to implementation

Grant Martin is a fellow at Cadence Berkeley Labs in Berkeley, Calif.
We have heard the commotion over SystemC and an evolved Verilog. The IEEE 1364 Verilog committee has a plan to specify next-generation Verilog: 1364-2005. Verilog 2005 will be based on input from vendors (such as Cadence Design Systems, which made several donations to IEEE 1364 this month), users (the worldwide Verilog community) and industry associations (such as Accellera, whose SystemVerilog 3.1 is slated for donation to IEEE in the near future).

Similarly, Open SystemC International has a well-formulated plan to standardize SystemC 2.1 via IEEE and will follow that up with further open-community work to evolve the language based on user needs.

Despite the press, which at times places the two languages in opposition, it is clear that Verilog and SystemC have complementary roles in moving designs from specification to implementation. SystemC is clearly a system design language, as my co-authors (Thorsten Grotker, Stan Liao and Stuart Swan) and I wrote in System Design with SystemC (Kluwer Academic Publishers, 2002).

SystemC lets design teams model and verify designs expressed at true system levels of abstraction, refine these to reflect implementation choices and, finally, link the system model to hardware implementation and verification. Using the concept of a functional virtual prototype, SystemC enables the creation of a transaction-level model of a design, allowing high-speed verification of systemwide testbenches.

Meanwhile, Verilog has shown itself to be one of the prime design implementation and verification hardware description languages, and the emergence of Verilog 2005 will strengthen those capabilities. Enhanced features for hardware specification and synthesis, verification testbench creation and other possibilities like intellectual property protection will reinforce the strengths of Verilog for advanced hardware design. Verilog 2005 will be able to link to design and verification models created in SystemC. Thus, hardware designers will be able to reuse system-level models to validate designs in their true system context.

That reinforces a point often forgotten about design languages: They have ceilings, as well as floors. Just as SystemC is not an optimal language for HDL and gate-level design, Verilog 2005 is not the right language for system-level modeling or for building high-performance functional virtual prototypes. It is the flow between languages, rather than the attempt to use a single language for all purposes, that enables a high-productivity and low-risk design process.

It is thus appropriate to remember that SystemC also has a ceiling. While it is evolving in its 3.0 version to include software task modeling and scheduling capabilities, it is not a software development environment. Recent developments in UML 2.0, to be finalized this year, promise greatly improved capabilities for system software modeling and code generation, especially for embedded real-time systems.

One promising area for future methodology work is to establish a truly trilingual world, where software specified in UML can generate platform-optimized software tasks that can be simulated within a SystemC-based transaction-level platform model. The hardware part of the design would be moved into Verilog 2005-based implementation and verification, reusing the functional prototypes built earlier in the process.

Peaceful coexistence is the goal for our truly multilingual world.

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