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Unifying ESL, verification

Posted: 01 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:design automation conference? electronic system level? design for verification? dft? esl?

According to some observers at the recent Design Automation Conference, the most important thing happening in EDA is electronic system level (ESL) design. Aart de Geus, Synopsys Inc. CEO, said the most important thing is "design for verification." It turns out these viewpoints are just different ways of looking at the same problem.

The core issue is that 90nm ICs can contain 100 million gates, and we don't have the technology to do 100-million-gate designs in any reasonable period of time. What will make it possible is very large IP block reuse. Not 50,000 gates, but a million or more gates. Not just memory, but also logic. Gary Smith, chief EDA analyst at Dataquest, sees ESL as the key to using those 100 million gates. Smith and other ESL advocates believe we have to move above RTL design and work at a higher level of abstraction, and that SystemC offers a standard way to do so.

De Geus views design for verification as a breakthrough on a par with the development of synthesis. "The design for verification age is taking off with SystemVerilog as the focal point," he said. SystemVerilog, he noted, provides a single language for design and verification, along with support for assertions, coverage and formal techniques.

These may seem like different visions, but look again. Where does ESL ultimately get us? Very large IP block reuse. Where does design for verification ultimately get us? Very large IP block reuse. As de Geus pointed out, the most important thing about IP reuse is verification. And as Smith noted in DAC presentations, what's really driving ESL is verification, not design creation.

We're going to need ESL and SystemC. But design for verification, with SystemVerilog, is the most obvious next step for most of today's RTL chip designers.

- Richard Goering

EE Times





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