Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Cadence platform to be deployed by Global Unichip

Posted: 04 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design? global unichip? virtual prototyping? signal integrity? timing closure?

Cadence Design Systems Inc. has announced that its Encounter Digital IC implementation platform has been selected by SoC design foundry Global Unichip Corp., as its hierarchical IC implementation platform.

The Cadence platform is expected to enable Unichip to address nanometer design challenges in its customer design services - specifically, virtual prototyping, routing, signal integrity (SI), and timing closure issues. The two companies have teamed up on a methodology project to build this advanced tape-out flow.

Article Comments - Cadence platform to be deployed by G...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top