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Xilinx DSPs support wireless infrastructures

Posted: 04 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? digital signal processing? intellectual property core? ip core? cdma2000?

Xilinx Inc. has released its digital signal processing (DSP) IP cores - CDMA2000/3GPP2 Turbo Convolutional Code (TCC) Encoder and Decoder, and DOCSIS ITU-T J.83 Annex B Modulator - that target wireless infrastructures as well as cable modem head-end equipment systems.

Designed for use with existing Xilinx FEC, multi-rate, and matched filter IP to build solutions for 3G wireless applications, the CDMA2000/3GPP2 TCC Encoder and Decoder implement MAX, MAX_SCALE, and MAX algorithms to allow tradeoffs between bit-error rate performance and complexity. The DOCSIS ITU-T J.83 Annex B Modulator provides a programmable digital baseband modulator for cable modem head-end equipment in North America.

The cores, when implemented on the Xilinx Spartan-3 and Virtex-II Pro FPGAs, are designed to provide the industry's lowest cost FPGA implementations for single or multi-channel systems. The license price for the CDMA2000 TCC encoder and decoder is $1,000 and $10,000, respectively, while the ITU-T J.83 Annex B Modulator has a license price of $2,000.





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