Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Actel revamps FPGA suite, tightens link to Synplify

Posted: 07 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:actel? libero? fpga? synplicity? synthesis software?

A new version of Actel Corp.'s Libero FPGA design environment is more tightly integrated with Synplicity Inc.'s synthesis software. It also has expanded interfaces to other vendors' tools and a floor planner with a multiview graphical user interface for the Actel Designer place and route environment.

Actel has been working with Synplicity to ensure that the latest version of the Synplify FPGA synthesis tool - which Actel bundles into its development systems - would help streamline the Libero flow, said Saloni Howard-Sarin, director of tool marketing at Actel. Actel has also improved its internally developed FPGA place and route software, to the point where the Libero suite generates a 60 percent performance improvement for Actel's flash-based ProASIC Plus family, she said.

"We focused on improving performance and ease of use throughout our entire flow to help customers reach timing closure more quickly with our ProASIC family," she said.

Actel and Synplicity worked together to coordinate Synplify's mapping and timing model capabilities to the ProASIC architecture. The synthesis improvements will deliver an 18 to 43 percent gain in run-times to customers, Howard-Sarin said.

Actel has also added new place and route algorithms to Libero v5.0, which tacks on a further 15 percent performance improvement, she said. And it has added interfaces for SynaptiCAD's WaveFormer Lite v9.0 and Mentor Graphics' ModelSim v5.7 tools.

Density vs. performance

Howard-Sarin said that Libero's place and route tool, Designer, has been enhanced. Its new floor planner, called ChipPlanner, lets users trade off between optimal design density and performance by managing regions, logic placement, I/O assignment, and routing. The new MultiView Navigator, meanwhile, simultaneously displays ChipPlanner, netlist, package, I/O attributes, hierarchy, and log window views. That lets users easily navigate a design and find bug sources more easily, she said.

Pricing for Libero v5.0 begins at $595. Actel Designer v5.0 begins at $995. Downloadable versions are available free from the company's website.

- Michael Santarini

EE Times

Article Comments - Actel revamps FPGA suite, tightens l...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top