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Zarlink analog PLL simplifies line card design

Posted: 08 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:zarlink semiconductor? analog PLL? zl30414?

Zarlink Semiconductor has unveiled an analog PLL timing chip for optical line cards operating at up to OC-192 rates. With six output clocks and high jitter performance, the ZL30414 device simplifies line card design and lowers space requirements.

Designed to perform timing and synchronization functions in communications equipment, including SONET/SDH line cards used in network core and access equipment, the analog PLL accepts input reference clock at 19.44MHz and provides six output clocks: four differential LVPECL clocks at 622.08MHz, a differential CML clock at 155.52MHz, and a 19.44MHz CMOS clock.

The four LVPECL clocks interface directly to line card devices such as framers, mappers, and serdes chips. By providing the logic level required by these devices, the ZL30414 eliminates the need for glue logic which is required when using most competing products.

Offered in a 64-pin TQFP, the chip measures 10-by-10mm, and is priced at $55.84 in quantities of 1,000.

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