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Averant lands patent for checking design properties

Posted: 12 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:averant? rtl static functional verification tool? verilog simulation?

RTL static functional verification tool vendor Averant Inc. has been issued a new patent by the U.S. Patent and Trademark Office (USPTO) for its method of computing the design coverage of a set of properties.

According to the company, the method, described in Patent No. 6,954,804, provides a quick and speedy way to verify whether a circuit design works as intended, augmenting traditional circuit verification techniques, such as Verilog simulation.

Averant's Solidify product allows users to develop a set of custom properties that are verified using Averant's static functional verification. The company claims that property verification is more exhaustive than simulation, and it does not require a testbench to specify stimuli.

Specifically, Averant's patent describes a method for determining whether users have developed enough properties to cover all aspects of the intended behavior.

- Michael Santarini

EE Times

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