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Silicon Metrics wins key patent

Posted: 12 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:silicon metrics? eda characterization? modeling software?

Silicon Metrics Corp. has won a U.S. patent on some of the core technology used in its EDA characterization and modeling software. The technology behind the patent allows the measurement of interdependent timing constraints on sequential cells.

The patent (No. 6,584,598) is titled "Apparatus and methods for constraint characterization with degradation options." Inventors of the patent are Guruprasad Rao, Silicon Metrics chief applications architect and co-founder, and Keith Howick, former product application engineer.

Before the development of this technology, according to Silicon Metrics, setup and hold constraints were measured independently. This is a problem at process technologies below 150nm, because constraints become more and more interdependent. The interdependency can cause regions of metastability, or unpredictability, that affects the timing, power, and functional characteristics of the chip.

The technology is used in Silicon Metrics' products, which provide characterization, modeling, and analysis tools for timing, power, and signal integrity. The tools are applied to standard cells, I/Os, and memories, and are used in design flows from Cadence Design Systems, Magma Design Automation, and Synopsys.

- Richard Goering

EE Times





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