Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Designers gravitate toward RTL sign-off

Posted: 13 Aug 2003 ?? ?Print Version ?Bookmark and Share

Keywords:rtl? asic? ic layout? physical-design tool? eda?

Support appears to be growing for RTL sign-off, a radical concept that would see mainstream ASIC designers bypass the synthesis and IC layout steps and sign off on a design at the register-transfer level. But this profound industry shift, expected to gain traction by the time feature sizes shrink to 65nm, depends on the development of new tools, especially the so-called silicon virtual prototype that accurately estimates what will be implemented in silicon.

RTL sign-off will be "bad news" for existing providers of IC implementation tools, said Gary Smith, chief EDA analyst at Gartner Dataquest. As designers move to electronic system-level tools and RTL sign-off, sales of today's RTL and physical-design tools will slow, he said.

But it's good news for silicon virtual prototype providers-one possible reason that EDA vendors such as Monterey Design Automation and Cadence Design Systems Inc. are mounting new efforts in this area. Meanwhile, ASIC vendors like IBM Microelectronics and LSI Logic Corp. are already taking RTL sign-offs on a selective basis.

Smith believes that the design-for-manufacturability (DFM) issues at 65nm are so daunting that only sophisticated power users, or ASIC vendors, will be able to handle physical implementation for chip designs. The mainstream users, he said, will start with system-level tools and stop at the silicon virtual prototype.

"At 65nm, the wall between design and manufacturing comes down," Smith said. "Most ASIC designers want that wall to be there. They're seeing all the problems they'll have at 65nm and saying they don't want any part of it."

Designers who implement chips at 65nm face formidable challenges. These include not only nanometer effects, such as IR drop and leakage current, but also process variability, which becomes much more of an issue as feature sizes shrink.

As a result, designers will need new statistical tools that help to predict and maximize yields, as well as new fault models and built-in test capabilities.

Smith's view has been controversial, but it is beginning to receive some support. Jeff Vanderlip, the director of ASIC technical marketing at LSI Logic Corp., said that it's "probably a fair statement" to assume that most ASIC designers will turn to RTL sign-off at 65nm. However, getting the right tools in place is critical, Vanderlip said. The list includes a silicon virtual prototype that can accurately predict die size and performance, as well as let customers write complete, accurate timing constraints, he said.

Aidan Kelly, manager of ASIC methodology at IBM Microelectronics, said he agrees "in general" with Smith's prediction. "As we extend below 90nm, design is going to get very, very difficult," he said. "It's not just area and timing; it's power, noise, yield, reliability and manufacturing. We're the ones closest to the technology, and my opinion is that below 90nm we'll do all the technology stuff."

"I think there will be a general shift," said Charlie Huang, VP of business development at Cadence Design Systems. "Ordinary users will probably move above the gate level to RTL with some prototyping."

Cadence's April purchase of Get2Chip Inc. is an important part of its strategy for building a silicon virtual prototype. According to Lavi Lev, executive vice president for Cadence's implementation division, such a tool includes two components-physical prototyping, and fast synthesis combined with a what-if analysis for placement and routing. Thus, the marriage of Silicon Perspectives' prototyping technology with Get2Chip's synthesis is an important step toward that goal.

Synopsys Inc. has a more skeptical view of RTL sign-off, seeing it as just one of several strategies that will be used below 100nm. While manufacturing issues will become critical at 65nm, the industry will develop solutions that address them in the IC implementation flow, said Gal Hasson, director of marketing for RTL and FPGA synthesis at Synopsys.

"Synopsys is currently engaged with our semiconductor partners to enhance our Galaxy design platform to become DFM-aware in order to allow designers to continue to employ their preferred implementation model at 65nm."

Monterey Design Automation, meanwhile, announced in July that it is refocusing to make Calypso, its upcoming virtual-prototyping tool, a flagship product.

Vendors including Icinergy, InTime, Magma Design Automation, Synopsys and Tera Systems are all working on design-planning as well as prototyping tools.

Both IBM and LSI Logic are starting to take RTL sign-offs today-but it's not a push-button process. IBM, said Kelly, is currently running pilot projects and seeing strong results. "RTL sign-off is not something that's ready for the mainstream, so we're being careful with the designs we take," he said.

IBM's RTL sign-off flow uses Tera Systems' TeraForm prototyping tool, along with IBM synthesis. This combination, said Kelly, yields good timing and area information, and provides enough information to build an RTL floor plan. However, the flow is currently aimed at designs that aren't very complex, and RTL power and IR drop analysis needs further development, he said.

LSI Logic, which also uses TeraForm, is taking RTL handoffs on a very selective basis, Vanderlip said. "We're careful to pick engagements we know will be successful, and they're limited in number because of resources."

With RTL sign-off, he noted, LSI Logic is doing more of the design. Further, there may be a need to improve or modify the RTL to meet design requirements. And even when LSI takes RTL code, it may hand the customer a gate-level netlist in order to do timing verification and sign off, he noted.

"A key issue is the designer's ability to generate and validate complete and accurate timing constraints before they sign off," Vanderlip pointed out. "A silicon virtual-prototyping tool would have to enable that. It's very difficult now."

Vanderlip said that no prototyping tool today is fast and accurate enough to enable a high volume of RTL handoffs.

But Vanderlip said he believes that technology is pushing the industry not only toward RTL sign-off, but possibly beyond, to what he calls "specification handovers" from a language such as C or SystemVerilog.

Still, one thing will not change, Vanderlip said: "ASIC engagements have been, and always will be, very interactive between the customer and the ASIC vendor."

- Richard Goering

EE Times

Article Comments - Designers gravitate toward RTL sign-...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top