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Improve the library, not the tools, to achieve timing closure

Posted: 01 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:physical synthesis? library? buffer up technique? gate? design tool?

Physical synthesis as a core technology is not needed everywhere, and surprisingly, by making some straightforward changes to the underlying cell library, timing closure can easily be achieved using simpler tools.

Physical synthesis is already a prevalent, albeit expensive, technology. During the mapping iteration in physical synthesis, the gates are placed and an approximate route performed. That lets the mapping better estimate the load of each gate and act accordingly. The result is a placement and global-route file.

The algorithms are necessarily approximate, since the major routing, back-annotation and timing iterations are now performed within the tool. Of course, physical synthesis is not a universal panacea; there may still be further iterations after detailed routing. But the hope is that the manual iterations will converge quickly.

In the simplest case, it is possible to use "buffer up" techniques to close timing on any circuit that only has inverters. There is one caveat: There must be enough space to grow some of the inverters. By using a simple wire load model, a coarse size grading is usually enough to minimize the effect of resizing. If cell utilization is high, then the placement area can be increased.

Why do circuits that only use inverters converge so well? The reason is that these simple cells tend naturally to have the same intrinsic (load-independent) delay, but with each size having a different slope (load-dependent) delay. Thus, the original synthesis delay can be matched by sizing alone.

Even real-world RC effects are easily catered to in the buffer-up world. In deep submicron, edge rate effects are also important. These can be managed using a simple averaging function during cell characterization that makes little difference to how the whole system converges.

Intrinsic delay

For gates with more than one input, the intrinsic delay in each gate family typically varies with drive strength, since cell libraries are designed to optimize cell area. Multiplexers and equivalence gates are good examples. During optimization, changing the gate strength (because the load was incorrectly guessed in the tool) can add large chunks of intrinsic delay, for which the only solution is to remap. Hence the need for physical synthesis, where load estimates improve with each iteration.

However, if the cell library is designed so that each gate family has the same intrinsic delay, then all cases degenerate to the simple inverter case. This requires some attention when building the library but is not difficult.

Some test cases using a standard processor (with a DSP co-processor) on 0.18?m and 0.13?m have been tried. The design contains numerous mux and exor trees, which are notoriously difficult for timing closure. Physical synthesis tools from all the CAD vendors were compared with use of the new library, DC and a standard place-and-route engine.

The results were surprising. The old toolset immediately converged to the most stringent constraints, whereas the highest speed was never met using physical synthesis, even after two or three manual iterations. Additionally, the area was significantly smaller (probably accounting for the increased speed), even though the new cell library was, in general, much larger.

The library approach not only adds an interesting way of extending the life and usage of older toolsets but, in combination with physical synthesis, could also offer a more potent solution.

- Anthony Mark Jones

EE Times





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