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Regulating processor power for sophisticated handhelds

Posted: 01 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:low power? power management? embedded processor? power consumption? battery?

Low-power consumption is one of the most important features of embedded processors and has a significant impact on the cost and physical size of the end-device.

The processor may not be the most power-hungry component of a system design but it is essential to manage processor power to reduce overall system power consumption. Improved processor power efficiency can increase the available power budget for features such as color screens and backlights, which are becoming standard features on wireless handsets, handheld gaming consoles and portable media players.

Historically, low-power consumption in embedded processors has been achieved through the use of a number of low-power idle and sleep modes. Embedded processors are now performing more sophisticated tasks that require ever-higher performance levels. As a result, new processor designs are now using sophisticated architectural techniques, such as branch prediction and speculation, to achieve high performance. However, these techniques can also significantly increase the processor's power consumption.

Although there have been incremental improvements in battery technology like increases in life and reduction in size, these changes are not keeping pace with the rapidly increasing power requirements of next-generation designs. Conventional power management is no longer sufficient to keep battery life at a level acceptable to end-users.

Process technology trends are also complicating the power story. Until recently, CMOS transistors consumed negligible amounts of power under static conditions. However, as process geometries shrink to provide increasing speed and density, their static (leakage) power consumption has also increased.

Current estimates suggest that static power accounts for about 15 percent to 20 percent of the total power on chips implemented in 0.13?m high-speed processes. Moreover, as process technology moves below 100nm, static power consumption is set to increase exponentially, and will soon dominate the total power consumed by the processor.

A way to bridge the gap between high-performance and low-power is to enable the processor to run at different performance levels depending on the current workload. An MPEG video player, for example, requires higher performance than an MP3 audio player. Hence, the processor could run at a much lower frequency for playing MP3 and still achieve accurate playback at full quality. Energy savings is achieved by reducing the processor's supply voltage as the clock frequency is reduced.

Dynamic voltage scaling (DVS) exploits the fact that the peak frequency of a processor implemented in CMOS is proportional to the supply voltage, while the amount of dynamic energy required for a given workload is proportional to the square of the processor's supply voltage. Reducing the supply voltage, while slowing the processor's clock frequency, yields a quadratic reduction in energy consumption at the cost of increased runtime. As the amount of energy stored in a battery is finite for each charging cycle, such energy conservation is the only method of extending battery life.

The Need for Control

A figure illustrates significantly lower total energy consumption over time using DVS compared with a conventional gated-clock power management scheme. Often, the processor is running too fast. For example, it is pointless from a QoS perspective to decode the 30 frames of a video in half a second, when the software is only required to display those frames during a one second interval. Completing a task before its deadline is an inefficient use of energy.

The key to taking advantage of this trade-off is the use of intelligent software that aims to reduce the processor's performance level to a point where it is just meeting the application software's deadlines. Such software should comprise of "performance-setting" algorithms that determine the optimum performance level to run at and then manage performance scaling techniques such a DVS to deliver that performance level.

ARM has been researching a solution for the intelligent control of performance scaling hardware and has now developed an end-to-end solution which is being offered to developers of battery-powered equipment.

The solution is based on the Intelligent Energy Manager (IEM) software component. The IEM interfaces to the OS running underneath the application software and uses key parameters taken from the internal structures of the OS to "instrument" the use of the OS by the applications currently running. A number of sophisticated software algorithms are used to evaluate different types of software activity and generate a prediction of future performance. The results of each prediction are combined using an evaluation stack to determine a global performance prediction.

Working closely with the IEM software is the Intelligent Energy Controller (IEC) component. Through the use of precision counters and timers, the IEC component works to measure the current performance level of the system and feeds this back to the software to ensure that the processor performance never drops below that needed to meet the deadlines of the software workload. Also, it offloads much of the instrumentation activity from the software into hardware, reducing the overhead of the IEM software on the processor.

The IEC component also provides an abstraction of the performance scaling hardware. From the software perspective, requests for a new performance level are issued to the IEC component as the workload changes and the predictions are revised. How this performance level is achieved is hidden from the software by the abstraction. The IEC component is configurable at design time to interface to an on-chip, design-specific clock management unit (CMU) and power controller components. The CMU is responsible for delivering a clock frequency to the processor that is related to the performance level requested.

Meanwhile, the power controller component is responsible for interfacing to an off-chip power supply that delivers a voltage to the processor core that is similarly related to the requested performance level. Coordination of changes to the clock frequency and voltage are managed by the IEC to ensure that valid combinations exist at all times and that the transitions between different performance levels are smooth and occur as fast as possible given the limitations of the clock generation scheme and external power supply.

Maximizing energy conservation

IEM technology was developed to help OEMs maximize the battery life of their handheld, battery-powered products. The "componentized" nature of the total solution means that the technology can be adapted to suit to underlying performance scaling hardware. The IEM prediction software determines the lowest performance level that the processor can run at while ensuring, with the aid of the IEC component, that software deadlines are never missed.

Today, driven by the IEC component, the APC works with the external EMU and takes this performance prediction to bring the processor to the lowest possible voltage and frequency. This full DVS solution reduces the energy consumed by the processor to the lowest possible, given the constraints of the clock generator, power supply dynamics and the headroom available in the mix of application software.

The use of 90nm and 70nm process geometries offers new opportunities for IEM technology. As the leakage current component of both dynamic and static energy consumption increases sharply, other performance scaling techniques become beneficial. Some examples are dynamic body biasing and threshold scaling. With their hardware-independent nature, the IEM and the IEC components are equally applicable to the management of these techniques.

- Clive Watts

Systems Product Manager


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