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Startup eyes hard/software pre-silicon validation

Posted: 03 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:carbon design systems? verification? validation tool? verilog? fpga prototyping?

A 15-person design automation startup staffed with verification veterans aims to make pre-silicon validation tools practical for the masses.

Carbon Design Systems Inc. says it will introduce a pre-silicon validation suite by year's end that adds software-level constructs to rough Verilog code to create a Verilog-based transaction model that can be read by most software development tools. The model can be distributed cheaply to a large number of software designers, giving them a jump on firmware, driver development, driver diagnostics and functional hardware debug, the company said.

"To date, presilicon validation has been impractical for most companies," said Stephen Butler, president and CEO of Carbon Design. "Validation with emulation and FPGA-based prototyping are cost-prohibitive and don't give hardware and especially software designers the true functionality of the ICs they are developing."

Though reluctant to reveal the details of his company's offering, Butler said Carbon's two-tool suite consists of a compiler technology that IC designers will use to transform their rough register-transfer-level code, cores, memories, and gates into an encrypted macro RTL model that can be distributed en masse to software designers.

Carbon's second tool, which will be sold to software developers receiving the models, is essentially a player/simulator that can link the macro RTL model to optimized cores, software and transactions in C, C++ and SystemC to support development. The player's application-programming interface allows users to run the "Carbonized" models on their software development environment of choice. The player also lets designers flag functional issues in hardware to indicate Verilog code that can be refined before proceeding to gates.

"We're allowing hardware designers to deliver fast, cycle-accurate, functionally correct models to software engineers very quickly," said Butler, who said that beta customers have already ordered the tools. The technology is attractive to big companies, he said, because it doesn't require retooling or a new methodology and can be distributed en masse to software designers. Carbon's technology is not an electronic system-level (ESL) tool suite, he said, but rather a software-based validation technology that can replace emulation replicates and FPGA breadboards.

Carbonized Verilog models run three to 50 times faster than vanilla Verilog models, Butler said. One customer started with a Verilog model of a 1.5 million-gate CPU running 112Hz; after compiling it with the Carbon technology, the design ran at 2,297Hz. In another application, a Verilog model of a 3 million-gate CPU system ASIC running at 93Hz was sped up to 1,091Hz after Carbon compilation.

Each model has a tiny footprint consumed mostly in cache, Butler said. The company has Carbonized a 25 million-gate design and believes it can handle designs above 100 million gates. The first version of the tool supports only Verilog, but Butler said subsequent versions will support VHDL and, after that, possibly SystemVerilog. "We think we are really on to something," said Butler, who believes the company will clear $1 million by year's end. Butler said he wants to direct Carbon Design toward an initial public offering down the road.

Carbon has garnered $5 million in venture funding from Flagship Ventures and Commonwealth Capital. Its management includes veterans from both the ESL and emulation worlds. Kevin Hotaling, a former sales executive at Quickturn and C Level Design, is vice president of sales. Founder Bill Neifert, a former applications manager at C Level Design, is chief technical officer. Josh Marantz, once Ikos' director of software engineering, is vice president of engineering. And Quickturn veteran Andy Ladd is director of product deployment.

- Michael Santarini

EE Times





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