Verilog won't diverge, user reps pledge

Although the IEEE and the Accellera standards organization appear to be heading in different directions with the next generation of Verilog, IEEE 1364 Working Group and Accellera's SystemVerilog committee members said they won't allow incompatible standards to emerge.

The IEEE 1364 Working Group, also known as the Verilog Standards Group (VSG), announced that the open period for technology donations to its forthcoming 1364-2005 (Verilog 2005) standard has ended. The group received nine technology donations from Cadence, Verisity, Fintronic, and Jeda Technologies - but nothing from Accellera, which is putting the finishing touches in SystemVerilog 3.1.

As a result, SystemVerilog 3.1 extensions - despite heavy backing from Synopsys Inc., and pledges of support from several EDA vendors - may not make it into an IEEE standard until 2009 or 2010, according to Mike McNamara, VSG chair. But consultants Stu Sutherland and Cliff Cummings, speaking for themselves rather than Accellera or the IEEE, said the door is still open for a unified standard.

Sutherland said the August deadline for technology submissions was needed in order to get the IEEE standard moving - but it's not a "do-or-die" proposition, he noted. The VSG can still consider technology donations submitted after the deadline, he said, if they're viewed as critical to Verilog users.

"I think most - indeed, I dare say all - of the 1364 committee recognizes that SystemVerilog is a critical set of enhancements to most Verilog users," Sutherland said. "I am convinced that SystemVerilog enhancements will become part of the IEEE 1364 Verilog standard."

"There will not be two Verilog standards," Sutherland said. "SystemVerilog, in my opinion, is really a prerelease of the next Verilog standard, with much-needed extensions that design and verification engineers need now, not two, three or five years from now."

"I do not believe we will end up with two incompatible Verilogs," said Cummings. "I estimate that half of the IEEE Verilog committee also works on the Accellera SystemVerilog committee, and none of us are going to let the two languages diverge."

"There are definitely IEEE-Accellera politics in play and I believe most committee members would like it to stop," he added.

McNamara said VSG could consider a post-deadline donation, but cannot guarantee its inclusion, and would have difficulty with anything more than a "small" donation. SystemVerilog is a "very large entity," he noted, and might have to wait for Verilog 2010 if it isn't donated soon. Accellera has provided no timetable for the donation.

SystemVerilog advocates note that the language is ready for implementation now, and IEEE 1364-2005 Verilog won't be ready for two years. Cummings said chip designers will start using SystemVerilog extensions as soon as their tools support them, which will be soon. Later on, he said, the IEEE features will be available, and users will employ those as well.

Still, committee members face one challenge: there is some overlap, and potentially some conflict, between some of the IEEE technology donations and features in SystemVerilog 3.1.

Versity, for example, is proposing extensions for test generation and functional coverage derived from its "e" language. SystemVerilog 3.1, in contrast, uses verification constructs derived from Synopsys' competing Vera language. Verisity's approach is also fundamentally different, said Steve Glaser, Verisity vice president of corporate marketing and business development.

What SystemVerilog 3.1 currently provides, Glaser said, is the "appendage" of another language onto Verilog. What's needed instead, he said, is a "smaller set of native extensions." Thus, he said, Verisity's proposal provides a simpler, cleaner approach to verification than what's currently in SystemVerilog 3.1.

"If you start adding lots of keywords, it's a nightmare in terms of legacy code," he said. "There are experts who think a lot of legacy code will break with the [SystemVerilog] approach being used."

While SystemVerilog 3.1 has a built-in assertion mechanism, Versity believes IEEE Verilog 2005 should use Accellera's Property Specification Language version 1.01 as the property specification language for Verilog.

Cadence Design Systems is proposing extensions for constrained and random testbenches that overlap with some of the SystemVerilog 3.1 extensions. According to Mitch Weaver, Cadence vice president of marketing, Cadence's philosophy is to provide extensions as Verilog libraries rather than as new keywords. Cadence has already implemented many of its proposed extensions, he said.

In Cummings' view, however, this will all be sorted out. "You may see different enhancements added by the different committees, but those of us who serve on both committees are making sure the different enhancements are not incompatible," he said.

- Richard Goering

EE Times