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Xilinx upgrades ISE FPGA design suite

Posted: 10 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? integrated software environment? ise? fpga design suite?

Xilinx Inc. has improved clock performance, software run-time and area utilization in its Integrated Software Environment (ISE) FPGA design suite.

Rich Sevcik, senior VP of FPGA products, said the company's small army of tool developers has added more than 250 improvements to version 6.1i of ISE. "The new suite delivers 31 percent faster performance and 15 percent better logic utilization than our nearest competitor," he said.

The three most notable enhancements were to the place and router engines, which on average gain 18 percent in clock frequency performance; to a new preplacement mapper that packs 23 percent more densely than the prior mapper; and to automatic pin placement that links pin placement directly to PCB tools from Cadence Design Systems Inc. and Mentor Graphics Corp., Sevcik said.

"We've done a lot of the usual enhancements to algorithms throughout our entire flow. But we went the extra mile in improving our placement and routing algorithms," he said.

The improvements allow the ISE 6.1i placement and routing engine to improve clock speed of designs implemented in Xilinx FPGAs, Sevcik said. It also allows a designer to create high-speed memory interfaces operating at over 200MHz via an automatic local clock routing utility.

The suite's new preplacement mapper is "the only timing-driven mapper in programmable logic today," Sevcik said. It maps an EDIF netlist based on timing, and can shrink a design's die size by 23 percent, leaving room to place extra functions on a Xilinx FPGA, he said.

"We've also worked with Cadence and Mentor PCB groups to ensure that pin-to-PCB assignment is automated," said Sevcik. "Once an FPGA is completed and pins are placed, that output can be automatically read by Cadence and Mentor tools. On small designs that wasn't a big deal, but on multiple thousand-pin designs that's a big deal, especially to PCB designers."

The company has also upgraded Pace, the Pinout and Area Constraints Editor. The utility now includes support for complex programmable logic devices and allows users to enter pin definitions before a hardware description language source design exists. That essentially eliminates the need to complete designs before going to PCB layout. Pace also supports comma-separated value (CSV) bidirectional file transfer, resulting in better integration with PCB layout design tools. "It means that PCB designers using Cadence and Xilinx don't have to enter pins manually," said Sevcik. "Pace does it automatically when the design is past its PCB layout."

Noting that FPGAs are reaching 500MHz to 600MHz, Sevcik said Xilinx has had to add pin delays and timing jitter constraints to the latest version of ISE.

The Pace utility now has package pin flight time reporting for source-synchronous designs, he said. "Because of the increasing speed of these devices, there are picosecond delays between die and package depending on the size and number of pins used," said Sevcik. "Users set up package pin flight time and, during pin placement, flight time is automatically taken into account."

Constraints for jitter can be input into the tool by users for higher frequency designs. The tool then automatically takes jitter effects into account in controlling timing.

The company has also improved the ChipScope real-time debugging tool so users can now do cross-triggering between their software debugger and ChipScope Pro. The company has also ensured with this version that the timing netlists and SDF files match original hierarchy.

Sevcik said the tool's Navigator advanced design-flow-based project manager lets users of synthesis tools from Synplicity and Xilinx mix VHDL and Verilog HDL source.

Users can also launch the Xilinx Embedded Design Kit XPS project manager, and use the Automatic Web Update feature, which monitors software updates, notifies users and can download the files necessary to keep a user's ISE configuration current.

The suite runs under RedHat Linux, Solaris, and Windows. Pricing for ISE starts at $695. A full-featured, time-limited evaluation version is available free at the Xilinx website.

- Michael Santarini

EE Times





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