Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Modeling tools aid in immersion litho quest

Posted: 11 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:sigma-c gmbh? wafer? modeling tool?

A German company is fielding modeling tools that can help chipmakers assess the promise of immersion lithography. Putting a layer of water between a wafer and the stepper lens could extend current 193nm lithographic exposure tools down to the 45nm chip-manufacturing node and below, experts believe.

"People want to decide this year whether to scrap their plans to go to some next-generation lithography technique like EUV (extreme ultraviolet), or to use immersion lithography," said Peter Brooks, applications support engineer with Sigma-C GmbH. "With EUV, you need to expose wafers in very cleanrooms, but with immersion you can just put a puddle of water between the lens and the wafer."

To help chip manufacturers make that decision, Sigma-C recently upgraded its Solid-C simulator to include "one-click" immersion. "The nice thing about our simulator is that you can click the mouse to turn immersion on and off," said Brooks. "You can try out 193nm with immersion and compare it to 157nm dry before you commit to anything."

The company also models increased depth of focus. Sigma-C simulates 3D wafer stack topography in conjunction with liquid immersion lithography and determines how the stepper will image the mask into the wafer, outputting a 3D resist "profile." From that engineers can measure to determine if their process is correct-all before a single chip is fabricated.

- R. Colin Johnson

EE Times





Article Comments - Modeling tools aid in immersion lith...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top