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Chip technologies from IBM promise faster transistors

Posted: 11 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:ibm? power device? transistor? silicon on insulator? soi?

IBM announced two milestones that could enable the IT industry to produce higher performing, lower power devices in the near future.

According to the company, it has developed the first transistor using strained silicon directly on insulator (SSDOI) technology. This method, a combination of the strained silicon and silicon on insulator (SOI) techniques, reputedly offers high performance while eliminating manufacturing problems. In addition, IBM has been able to combine two different underlying silicon layers that simultaneously maximize the performance of the key transistors used in CMOS devices, which are the foundation for everything from cell phones to PCs to supercomputers.

CMOS technology, a high performance, low-power chip, has been widely used in electronic devices because it's been scaleable on a path following Moore's Law the past three decades. However, continuing this CMOS performance trend has become extremely difficult because the industry is approaching the fundamental physical limits of CMOS scaling.

"These two innovative techniques are relatively simple to implement using standard wafer processing techniques," said Dr. T.C. Chen, VP Science and Technology, IBM Research. "Implementing either could provide the industry with higher performing and lower power chips; combining the techniques could generate even higher performance and lower power," he explained.

Two technologies explained

The industry is now aggressively seeking new ways to make electric charges move faster through device channels because doing so increases circuit speeds and reduces power consumption. Strained silicon technology provides high electron mobility by stretching the top silicon layer with an underlying layer of silicon germanium (SiGe). IBM has previously reported a 20-30 percent performance enhancement using strained silicon.

However, the presence of a SiGe layer causes material and process integration challenges. IBM is the first to fabricate transistors using ultra-thin SSDOI structures that bypass this SiGe layer, thereby providing high electron mobility while eliminating material and process integration problems.

Another way to improve CMOS performance is to increase the mobility of its positive charges, or holes, through the device channels. IBM has been able to integrate devices with 2.5 times higher hole mobility into conventional CMOS technology by combining two substrates in the same wafer. This resulted in a 40-65 percent performance enhancement, says IBM.





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