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Silicon 'debug' product serves Synopsys DFT users

Posted: 15 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:synopsys? design for test? dft? intellitech? nebula silicon debugger?

Claiming to dramatically speed test vector debug time for users of Synopsys' design for test (DFT) products, Intellitech Corp. has announced the Nebula silicon debugger. It claims to understand the automatic test pattern generation (ATPG) produced by Synopsys TetraMax product, as well as the test structures inserted by Synopsys' BSD Compiler and DFT Compiler.

Nebula allows remote testing of prototype silicon for stuck-at faults, path-delay faults, at-speed built-in self test, and in-situ functional debug. Access to the TetraMax database dictionary allows users to quickly isolate failures to the gate and net level, Intellitech claims.

Nebula touts a "smart tester" architecture that understands the difference between serial scan test data and parallel pin test data, allowing the engineer to debug using functional elements of the design rather than counting bits from tester channel results. After applying test patterns, Nebula can program an on-chip volatile memory with data to disable the faulty area and enable a redundant logic area.

Nebula interfaces to an IC using standard test protocols, such as muxed scan, level-sensitive scan design or IEEE 1149.1. It provides software support for external instruments, such as power supplies, frequency generators, RF signal generators, and thermal chambers. Nebula is available now starting at $50,000 for desktop hardware and a floating license.

- Richard Goering

EE Times





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