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Register-transfer level design handoff is ready

Posted: 16 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:rtl? soc? moore's law? hdl? design handoff?

A significant paradigm shift in design methodology is taking place with RTL design handoff. Shrinking process nodes, increasing SoC design complexities and tightened purse strings have made the venerable "gate-level design sign-off" unacceptable, particularly in light of the wasted time and money associated with synthesis/place-and-route design iterations. SoC designers need to operate more efficiently, reduce design costs and accelerate design turnaround times, which can all be accomplished by moving more of their design to RTL.

The gap between chip-manufacturing capability (Moore's Law) and design capacity - the so-called design gap - is accelerating with advances in processing technology. Keeping up with Moore's Law requires the implementation of disruptive design technology every few years. A common theme of advancing design technology is the continuing move to higher design-abstraction levels. In addition, each disruptive design-technology shift creates a retooling cycle and results in a new EDA market leader - this occurs every five to eight years.

Similar to when schematic entry yielded to HDL-based design input, indicating the shift from transistor-level to gate-level design, gate-level tools have run out of steam. Shrinking design nodes have resulted in interconnect delays dominating on-chip timing. The statistical wiring estimates on which logic-synthesis tools relied to optimize a design's timing became unusable several years ago. Even traditional floorplan-derived wiring estimates are not accurate enough for chips implemented with 130nm processes and below.

Over-designing the chip accounts for inaccurate timing estimates, and hence wastes silicon and power. Using synthesis/place-and-route iterations to converge on a chip's timing and other specifications is time-consuming and expensive. Problems are detected late and too much unpredictability is added to the chip's design schedule. In addition, synthesis does not handle other specifications, such as signal integrity and reliability, very well. Designers need more comprehensive up-front analysis and earlier visibility into the physical effects of the design.

Recent design-tool and methodology enhancements, such as physical synthesis and unified RTL-to-layout tools and design flows, do not solve the problems of wasted time and money during complex chip designs. These tools are expensive and still do not provide early design-feasibility analysis. Furthermore, such tools have long runtimes and require front-end designers to have back-end (physical) knowledge.

Continuing advancements in process technology demand raising SoC design to a higher plane - RTL. Designers must identify downstream problems--timing, signal integrity, reliability and others - prior to synthesis, and be able to implement design fixes where they will have a more significant impact on chip performance. The key to a successful design is closure, not just meeting timing specifications. The various performance specifications comprising timing, power and reliability, along with chip cost, are all closely coupled, requiring an RTL design environment that can concurrently deal with and optimize all of these design considerations.

Successful RTL design predictability and correction - leading to a high-value RTL design handoff - require accurate RTL silicon virtual-prototyping (SVP) tools. These tools predict post-layout behavior prior to expensive synthesis/place-and-route operations, fixing problems at RTL and guiding the downstream synthesis/place-and-route tools. Design corrections at RTL have a more significant performance impact than those implemented at the gate level or further down the design chain. In addition, solving the problem at RTL costs less than it would later in the design cycle.

RTL design is also closer to the system-level design specification, which assists system architects in conveying design intent from the system level. Other benefits of working at RTL are less design complexity than at the gate level and that RTL design and analysis tools run orders of magnitude faster than gate-level tools. Since RTL design impacts back-end operations, good SVP tools at this level can influence design-for-manufacturability as well as performance decisions.

RTL tool interoperability allows companies to use their own back-end design tools and leverage existing back-end tools. The success of these companies is paving the way for RTL design handoff to become a necessary part of successful design, both with ASIC and customer-owned tooling designs, complementing downstream sign-off but with the advantage of identifying and solving potential problems faster.

At a 2003 Design Automation Conference panel discussing the inadequacies of front-end/back-end design handoff, Roger Carpenter, a senior engineering manager at Broadcom, states that the terms front-end and back-end are obsolete when applied to the creation of complex chips. He feels that 'specification' and 'implementation' should replace these terms. RTL SVP tools will become the new specification front-end of SoC design, with the new implementation back-end comprising merged logic-synthesis and physical-implementation tools.


RTL design handoff will mark the transition between this new generation of front-end and back-end tools. During front-end design specification, RTL architectural investigation and design analysis will guide the designer in obtaining a viable design architecture that will meet chip requirements. The new, merged logic-synthesis/physical-implementation back-end is a far more efficient way to optimize the design than going through multiple synthesis/place-and-route cycles, with each tool attempting to perform its own optimization operations.

The end-result is a design flow that saves time and money compared to today's gate-level-centric way of designing chips. The availability of proven virtual-prototyping tools at RTL will fuel the accelerated design productivity of this new flow, making it possible to narrow the chip design gap and keep pace with continuing process and silicon-IP enhancements.

- Alain Labat

President and CEO

Tera Systems Inc.

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